CMSIS Cortex Device Peripheral Access Layer Header File. This file contains all the peripheral register's definitions, bits definitions and memory mapping for stm32wl55xx devices. More...

#include "core_cm4.h"
#include "system_stm32wlxx.h"
#include <stdint.h>

Data Structures
struct	ADC_TypeDef
	Analog to Digital Converter. More...

struct	ADC_Common_TypeDef

struct	AES_TypeDef
	AES hardware accelerator. More...

struct	COMP_TypeDef
	Comparator. More...

struct	COMP_Common_TypeDef

struct	CRC_TypeDef
	CRC calculation unit. More...

struct	DAC_TypeDef
	Digital to Analog Converter. More...

struct	DBGMCU_TypeDef
	Debug MCU. More...

struct	DMA_Channel_TypeDef
	DMA Controller. More...

struct	DMA_TypeDef

struct	DMAMUX_Channel_TypeDef
	DMA Multiplexer. More...

struct	DMAMUX_ChannelStatus_TypeDef

struct	DMAMUX_RequestGen_TypeDef

struct	DMAMUX_RequestGenStatus_TypeDef

struct	EXTI_TypeDef
	Async Interrupts and Events Controller. More...

struct	FLASH_TypeDef
	FLASH Registers. More...

struct	GPIO_TypeDef
	General Purpose I/O. More...

struct	GTZC_TZSC_TypeDef
	Global Security Controller. More...

struct	GTZC_TZIC_TypeDef

struct	HSEM_TypeDef
	HW Semaphore HSEM. More...

struct	HSEM_Common_TypeDef

struct	I2C_TypeDef
	Inter-integrated Circuit Interface. More...

struct	IPCC_TypeDef
	Inter-Processor Communication. More...

struct	IPCC_CommonTypeDef

struct	IWDG_TypeDef
	Independent WATCHDOG. More...

struct	LPTIM_TypeDef
	LPTIMER. More...

struct	PKA_TypeDef
	Public Key Accelerator (PKA) More...

struct	PWR_TypeDef
	Power Control. More...

struct	RCC_TypeDef
	Reset and Clock Control. More...

struct	RNG_TypeDef
	RNG. More...

struct	RTC_TypeDef
	Real-Time Clock. More...

struct	SPI_TypeDef
	Serial Peripheral Interface. More...

struct	SYSCFG_TypeDef
	System configuration controller. More...

struct	TAMP_TypeDef
	Tamper and backup registers. More...

struct	TIM_TypeDef
	TIM. More...

struct	USART_TypeDef
	Universal Synchronous Asynchronous Receiver Transmitter. More...

struct	VREFBUF_TypeDef
	VREFBUF. More...

struct	WWDG_TypeDef
	Window WATCHDOG. More...

struct	RSSLIB_pFunc_TypeDef
	RSSLib function pointer structure. More...

Macros
#define	DUAL_CORE

#define	__CM4_REV 1U
	Configuration of the Cortex-M4 Processor and Core Peripherals.

#define	__MPU_PRESENT 1U

#define	__VTOR_PRESENT 1U

#define	__NVIC_PRIO_BITS 4U

#define	__Vendor_SysTickConfig 0U

#define	__FPU_PRESENT 0U

#define	RTC_BACKUP_NB 20u
	RTC Specific device feature definitions.

#define	RTC_TAMP_NB 3u

#define	FLASH_BASE 0x08000000UL

#define	SYSTEM_FLASH_BASE 0x1FFF0000UL

#define	SRAM1_BASE 0x20000000UL

#define	SRAM2_BASE 0x20008000UL

#define	PERIPH_BASE 0x40000000UL

#define	FLASH_SIZE (((((uint32_t )FLASHSIZE_BASE)) & 0xFFFFU) << 10U)

#define	SRAM1_SIZE 0x00008000UL

#define	SRAM2_SIZE 0x00008000UL

#define	RSSLIB_PFUNC_BASE (SYSTEM_FLASH_BASE + 0x00003A00UL)

#define	OTP_AREA_BASE (SYSTEM_FLASH_BASE + 0x00007000UL)

#define	ENGI_BYTES_BASE (SYSTEM_FLASH_BASE + 0x00007400UL)

#define	OPTION_BYTES_BASE (SYSTEM_FLASH_BASE + 0x00007800UL)

#define	PACKAGE_BASE (ENGI_BYTES_BASE + 0x00000100UL)

#define	UID64_BASE (ENGI_BYTES_BASE + 0x00000180UL)

#define	UID_BASE (ENGI_BYTES_BASE + 0x00000190UL)

#define	FLASHSIZE_BASE (ENGI_BYTES_BASE + 0x000001E0UL)

#define	SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL)

#define	OTP_AREA_END_ADDR (0x1FFF73FFUL)

#define	ENGI_BYTE_END_ADDR (0x1FFF77FFUL)

#define	OPTION_BYTE_END_ADDR (0x1FFF7FFFUL)

#define	APB1PERIPH_BASE PERIPH_BASE

#define	APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)

#define	AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)

#define	AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)

#define	AHB3PERIPH_BASE (PERIPH_BASE + 0x18000000UL)

#define	APB3PERIPH_BASE (PERIPH_BASE + 0x18010000UL)

#define	TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL)

#define	RTC_BASE (APB1PERIPH_BASE + 0x00002800UL)

#define	WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL)

#define	IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL)

#define	SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL)

#define	USART2_BASE (APB1PERIPH_BASE + 0x00004400UL)

#define	I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL)

#define	I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL)

#define	I2C3_BASE (APB1PERIPH_BASE + 0x00005C00UL)

#define	DAC_BASE (APB1PERIPH_BASE + 0x00007400UL)

#define	LPTIM1_BASE (APB1PERIPH_BASE + 0x00007C00UL)

#define	LPUART1_BASE (APB1PERIPH_BASE + 0x00008000UL)

#define	LPTIM2_BASE (APB1PERIPH_BASE + 0x00009400UL)

#define	LPTIM3_BASE (APB1PERIPH_BASE + 0x00009800UL)

#define	TAMP_BASE (APB1PERIPH_BASE + 0x0000B000UL)

#define	SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000UL)

#define	VREFBUF_BASE (APB2PERIPH_BASE + 0x00000030UL)

#define	COMP1_BASE (APB2PERIPH_BASE + 0x00000200UL)

#define	COMP2_BASE (APB2PERIPH_BASE + 0x00000204UL)

#define	ADC_BASE (APB2PERIPH_BASE + 0x00002400UL)

#define	ADC_COMMON_BASE (APB2PERIPH_BASE + 0x00002708UL)

#define	TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL)

#define	SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL)

#define	USART1_BASE (APB2PERIPH_BASE + 0x00003800UL)

#define	TIM16_BASE (APB2PERIPH_BASE + 0x00004400UL)

#define	TIM17_BASE (APB2PERIPH_BASE + 0x00004800UL)

#define	DMA1_BASE (AHB1PERIPH_BASE + 0x00000000UL)

#define	DMA2_BASE (AHB1PERIPH_BASE + 0x00000400UL)

#define	DMAMUX1_BASE (AHB1PERIPH_BASE + 0x00000800UL)

#define	CRC_BASE (AHB1PERIPH_BASE + 0x00003000UL)

#define	DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL)

#define	DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL)

#define	DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)

#define	DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)

#define	DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)

#define	DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL)

#define	DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL)

#define	DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL)

#define	DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL)

#define	DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL)

#define	DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL)

#define	DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL)

#define	DMA2_Channel6_BASE (DMA2_BASE + 0x0000006CUL)

#define	DMA2_Channel7_BASE (DMA2_BASE + 0x00000080UL)

#define	DMAMUX1_Channel0_BASE (DMAMUX1_BASE)

#define	DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004UL)

#define	DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008UL)

#define	DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000CUL)

#define	DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010UL)

#define	DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x00000014UL)

#define	DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x00000018UL)

#define	DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x0000001CUL)

#define	DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x00000020UL)

#define	DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x00000024UL)

#define	DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x00000028UL)

#define	DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x0000002CUL)

#define	DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x00000030UL)

#define	DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x00000034UL)

#define	DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100UL)

#define	DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104UL)

#define	DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108UL)

#define	DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010CUL)

#define	DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL)

#define	DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL)

#define	IOPORT_BASE (AHB2PERIPH_BASE + 0x00000000UL)

#define	GPIOA_BASE (IOPORT_BASE + 0x00000000UL)

#define	GPIOB_BASE (IOPORT_BASE + 0x00000400UL)

#define	GPIOC_BASE (IOPORT_BASE + 0x00000800UL)

#define	GPIOH_BASE (IOPORT_BASE + 0x00001C00UL)

#define	PWR_BASE (AHB3PERIPH_BASE + 0x00000400UL)

#define	EXTI_BASE (AHB3PERIPH_BASE + 0x00000800UL)

#define	IPCC_BASE (AHB3PERIPH_BASE + 0x00000C00UL)

#define	RCC_BASE (AHB3PERIPH_BASE + 0x00000000UL)

#define	RNG_BASE (AHB3PERIPH_BASE + 0x00001000UL)

#define	HSEM_BASE (AHB3PERIPH_BASE + 0x00001400UL)

#define	AES_BASE (AHB3PERIPH_BASE + 0x00001800UL)

#define	PKA_BASE (AHB3PERIPH_BASE + 0x00002000UL)

#define	FLASH_REG_BASE (AHB3PERIPH_BASE + 0x00004000UL)

#define	GTZC_TZSC_BASE (AHB3PERIPH_BASE + 0x00004400UL)

#define	GTZC_TZIC_BASE (AHB3PERIPH_BASE + 0x00004800UL)

#define	SUBGHZSPI_BASE (APB3PERIPH_BASE + 0x00000000UL)

#define	DBGMCU_BASE (0xE0042000UL)

#define	TIM2 ((TIM_TypeDef *) TIM2_BASE)

#define	IWDG ((IWDG_TypeDef *) IWDG_BASE)

#define	WWDG ((WWDG_TypeDef *) WWDG_BASE)

#define	DAC ((DAC_TypeDef *) DAC_BASE)

#define	LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)

#define	LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)

#define	LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)

#define	RTC ((RTC_TypeDef *) RTC_BASE)

#define	SPI2 ((SPI_TypeDef *) SPI2_BASE)

#define	I2C1 ((I2C_TypeDef *) I2C1_BASE)

#define	I2C2 ((I2C_TypeDef *) I2C2_BASE)

#define	I2C3 ((I2C_TypeDef *) I2C3_BASE)

#define	TAMP ((TAMP_TypeDef *) TAMP_BASE)

#define	USART2 ((USART_TypeDef *) USART2_BASE)

#define	LPUART1 ((USART_TypeDef *) LPUART1_BASE)

#define	SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)

#define	VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)

#define	COMP1 ((COMP_TypeDef *) COMP1_BASE)

#define	COMP2 ((COMP_TypeDef *) COMP2_BASE)

#define	COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)

#define	TIM1 ((TIM_TypeDef *) TIM1_BASE)

#define	SPI1 ((SPI_TypeDef *) SPI1_BASE)

#define	ADC ((ADC_TypeDef *) ADC_BASE)

#define	ADC_COMMON ((ADC_Common_TypeDef *) ADC_COMMON_BASE)

#define	TIM16 ((TIM_TypeDef *) TIM16_BASE)

#define	TIM17 ((TIM_TypeDef *) TIM17_BASE)

#define	USART1 ((USART_TypeDef *) USART1_BASE)

#define	DMA1 ((DMA_TypeDef *) DMA1_BASE)

#define	DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)

#define	DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)

#define	DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)

#define	DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)

#define	DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)

#define	DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)

#define	DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)

#define	DMA2 ((DMA_TypeDef *) DMA2_BASE)

#define	DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)

#define	DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)

#define	DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)

#define	DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)

#define	DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)

#define	DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)

#define	DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)

#define	DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)

#define	DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)

#define	DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)

#define	DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)

#define	DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)

#define	DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)

#define	DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)

#define	DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)

#define	DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)

#define	DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)

#define	DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)

#define	DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)

#define	DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)

#define	DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)

#define	DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)

#define	DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)

#define	DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)

#define	DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)

#define	DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)

#define	DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)

#define	DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)

#define	CRC ((CRC_TypeDef *) CRC_BASE)

#define	GPIOA ((GPIO_TypeDef *) GPIOA_BASE)

#define	GPIOB ((GPIO_TypeDef *) GPIOB_BASE)

#define	GPIOC ((GPIO_TypeDef *) GPIOC_BASE)

#define	GPIOH ((GPIO_TypeDef *) GPIOH_BASE)

#define	AES ((AES_TypeDef *) AES_BASE)

#define	EXTI ((EXTI_TypeDef *) EXTI_BASE)

#define	IPCC ((IPCC_TypeDef *) IPCC_BASE)

#define	IPCC_C1 ((IPCC_CommonTypeDef *) IPCC_BASE)

#define	IPCC_C2 ((IPCC_CommonTypeDef *) (IPCC_BASE + 0x10U))

#define	RCC ((RCC_TypeDef *) RCC_BASE)

#define	PWR ((PWR_TypeDef *) PWR_BASE)

#define	RNG ((RNG_TypeDef *) RNG_BASE)

#define	HSEM ((HSEM_TypeDef *) HSEM_BASE)

#define	HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100U))

#define	PKA ((PKA_TypeDef *) PKA_BASE)

#define	FLASH ((FLASH_TypeDef *) FLASH_REG_BASE)

#define	GTZC_TZSC ((GTZC_TZSC_TypeDef *) GTZC_TZSC_BASE)

#define	GTZC_TZIC ((GTZC_TZIC_TypeDef *) GTZC_TZIC_BASE)

#define	SUBGHZSPI ((SPI_TypeDef *) SUBGHZSPI_BASE)

#define	DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)

#define	LSI_STARTUP_TIME 130U

#define	ADC_ISR_ADRDY_Pos (0U)

#define	ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos)

#define	ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk

#define	ADC_ISR_EOSMP_Pos (1U)

#define	ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos)

#define	ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk

#define	ADC_ISR_EOC_Pos (2U)

#define	ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos)

#define	ADC_ISR_EOC ADC_ISR_EOC_Msk

#define	ADC_ISR_EOS_Pos (3U)

#define	ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos)

#define	ADC_ISR_EOS ADC_ISR_EOS_Msk

#define	ADC_ISR_OVR_Pos (4U)

#define	ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos)

#define	ADC_ISR_OVR ADC_ISR_OVR_Msk

#define	ADC_ISR_AWD1_Pos (7U)

#define	ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos)

#define	ADC_ISR_AWD1 ADC_ISR_AWD1_Msk

#define	ADC_ISR_AWD2_Pos (8U)

#define	ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos)

#define	ADC_ISR_AWD2 ADC_ISR_AWD2_Msk

#define	ADC_ISR_AWD3_Pos (9U)

#define	ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos)

#define	ADC_ISR_AWD3 ADC_ISR_AWD3_Msk

#define	ADC_ISR_EOCAL_Pos (11U)

#define	ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos)

#define	ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk

#define	ADC_ISR_CCRDY_Pos (13U)

#define	ADC_ISR_CCRDY_Msk (0x1UL << ADC_ISR_CCRDY_Pos)

#define	ADC_ISR_CCRDY ADC_ISR_CCRDY_Msk

#define	ADC_IER_ADRDYIE_Pos (0U)

#define	ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos)

#define	ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk

#define	ADC_IER_EOSMPIE_Pos (1U)

#define	ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos)

#define	ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk

#define	ADC_IER_EOCIE_Pos (2U)

#define	ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos)

#define	ADC_IER_EOCIE ADC_IER_EOCIE_Msk

#define	ADC_IER_EOSIE_Pos (3U)

#define	ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos)

#define	ADC_IER_EOSIE ADC_IER_EOSIE_Msk

#define	ADC_IER_OVRIE_Pos (4U)

#define	ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos)

#define	ADC_IER_OVRIE ADC_IER_OVRIE_Msk

#define	ADC_IER_AWD1IE_Pos (7U)

#define	ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos)

#define	ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk

#define	ADC_IER_AWD2IE_Pos (8U)

#define	ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos)

#define	ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk

#define	ADC_IER_AWD3IE_Pos (9U)

#define	ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos)

#define	ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk

#define	ADC_IER_EOCALIE_Pos (11U)

#define	ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos)

#define	ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk

#define	ADC_IER_CCRDYIE_Pos (13U)

#define	ADC_IER_CCRDYIE_Msk (0x1UL << ADC_IER_CCRDYIE_Pos)

#define	ADC_IER_CCRDYIE ADC_IER_CCRDYIE_Msk

#define	ADC_CR_ADEN_Pos (0U)

#define	ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos)

#define	ADC_CR_ADEN ADC_CR_ADEN_Msk

#define	ADC_CR_ADDIS_Pos (1U)

#define	ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos)

#define	ADC_CR_ADDIS ADC_CR_ADDIS_Msk

#define	ADC_CR_ADSTART_Pos (2U)

#define	ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos)

#define	ADC_CR_ADSTART ADC_CR_ADSTART_Msk

#define	ADC_CR_ADSTP_Pos (4U)

#define	ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos)

#define	ADC_CR_ADSTP ADC_CR_ADSTP_Msk

#define	ADC_CR_ADVREGEN_Pos (28U)

#define	ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos)

#define	ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk

#define	ADC_CR_ADCAL_Pos (31U)

#define	ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos)

#define	ADC_CR_ADCAL ADC_CR_ADCAL_Msk

#define	ADC_CFGR1_DMAEN_Pos (0U)

#define	ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos)

#define	ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk

#define	ADC_CFGR1_DMACFG_Pos (1U)

#define	ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos)

#define	ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk

#define	ADC_CFGR1_SCANDIR_Pos (2U)

#define	ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos)

#define	ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk

#define	ADC_CFGR1_RES_Pos (3U)

#define	ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos)

#define	ADC_CFGR1_RES ADC_CFGR1_RES_Msk

#define	ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos)

#define	ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos)

#define	ADC_CFGR1_ALIGN_Pos (5U)

#define	ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos)

#define	ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk

#define	ADC_CFGR1_EXTSEL_Pos (6U)

#define	ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos)

#define	ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk

#define	ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos)

#define	ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos)

#define	ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos)

#define	ADC_CFGR1_EXTEN_Pos (10U)

#define	ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos)

#define	ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk

#define	ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos)

#define	ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos)

#define	ADC_CFGR1_OVRMOD_Pos (12U)

#define	ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos)

#define	ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk

#define	ADC_CFGR1_CONT_Pos (13U)

#define	ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos)

#define	ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk

#define	ADC_CFGR1_WAIT_Pos (14U)

#define	ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos)

#define	ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk

#define	ADC_CFGR1_AUTOFF_Pos (15U)

#define	ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos)

#define	ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk

#define	ADC_CFGR1_DISCEN_Pos (16U)

#define	ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos)

#define	ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk

#define	ADC_CFGR1_CHSELRMOD_Pos (21U)

#define	ADC_CFGR1_CHSELRMOD_Msk (0x1UL << ADC_CFGR1_CHSELRMOD_Pos)

#define	ADC_CFGR1_CHSELRMOD ADC_CFGR1_CHSELRMOD_Msk

#define	ADC_CFGR1_AWD1SGL_Pos (22U)

#define	ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos)

#define	ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk

#define	ADC_CFGR1_AWD1EN_Pos (23U)

#define	ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos)

#define	ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk

#define	ADC_CFGR1_AWD1CH_Pos (26U)

#define	ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos)

#define	ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk

#define	ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos)

#define	ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos)

#define	ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos)

#define	ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos)

#define	ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos)

#define	ADC_CFGR2_OVSE_Pos (0U)

#define	ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos)

#define	ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk

#define	ADC_CFGR2_OVSR_Pos (2U)

#define	ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos)

#define	ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk

#define	ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos)

#define	ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos)

#define	ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos)

#define	ADC_CFGR2_OVSS_Pos (5U)

#define	ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos)

#define	ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk

#define	ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos)

#define	ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos)

#define	ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos)

#define	ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos)

#define	ADC_CFGR2_TOVS_Pos (9U)

#define	ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos)

#define	ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk

#define	ADC_CFGR2_LFTRIG_Pos (29U)

#define	ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos)

#define	ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk

#define	ADC_CFGR2_CKMODE_Pos (30U)

#define	ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos)

#define	ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk

#define	ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos)

#define	ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos)

#define	ADC_SMPR_SMP1_Pos (0U)

#define	ADC_SMPR_SMP1_Msk (0x7UL << ADC_SMPR_SMP1_Pos)

#define	ADC_SMPR_SMP1 ADC_SMPR_SMP1_Msk

#define	ADC_SMPR_SMP1_0 (0x1UL << ADC_SMPR_SMP1_Pos)

#define	ADC_SMPR_SMP1_1 (0x2UL << ADC_SMPR_SMP1_Pos)

#define	ADC_SMPR_SMP1_2 (0x4UL << ADC_SMPR_SMP1_Pos)

#define	ADC_SMPR_SMP2_Pos (4U)

#define	ADC_SMPR_SMP2_Msk (0x7UL << ADC_SMPR_SMP2_Pos)

#define	ADC_SMPR_SMP2 ADC_SMPR_SMP2_Msk

#define	ADC_SMPR_SMP2_0 (0x1UL << ADC_SMPR_SMP2_Pos)

#define	ADC_SMPR_SMP2_1 (0x2UL << ADC_SMPR_SMP2_Pos)

#define	ADC_SMPR_SMP2_2 (0x4UL << ADC_SMPR_SMP2_Pos)

#define	ADC_SMPR_SMPSEL_Pos (8U)

#define	ADC_SMPR_SMPSEL_Msk (0x3FFFFUL << ADC_SMPR_SMPSEL_Pos)

#define	ADC_SMPR_SMPSEL ADC_SMPR_SMPSEL_Msk

#define	ADC_SMPR_SMPSEL0_Pos (8U)

#define	ADC_SMPR_SMPSEL0_Msk (0x1UL << ADC_SMPR_SMPSEL0_Pos)

#define	ADC_SMPR_SMPSEL0 ADC_SMPR_SMPSEL0_Msk

#define	ADC_SMPR_SMPSEL1_Pos (9U)

#define	ADC_SMPR_SMPSEL1_Msk (0x1UL << ADC_SMPR_SMPSEL1_Pos)

#define	ADC_SMPR_SMPSEL1 ADC_SMPR_SMPSEL1_Msk

#define	ADC_SMPR_SMPSEL2_Pos (10U)

#define	ADC_SMPR_SMPSEL2_Msk (0x1UL << ADC_SMPR_SMPSEL2_Pos)

#define	ADC_SMPR_SMPSEL2 ADC_SMPR_SMPSEL2_Msk

#define	ADC_SMPR_SMPSEL3_Pos (11U)

#define	ADC_SMPR_SMPSEL3_Msk (0x1UL << ADC_SMPR_SMPSEL3_Pos)

#define	ADC_SMPR_SMPSEL3 ADC_SMPR_SMPSEL3_Msk

#define	ADC_SMPR_SMPSEL4_Pos (12U)

#define	ADC_SMPR_SMPSEL4_Msk (0x1UL << ADC_SMPR_SMPSEL4_Pos)

#define	ADC_SMPR_SMPSEL4 ADC_SMPR_SMPSEL4_Msk

#define	ADC_SMPR_SMPSEL5_Pos (13U)

#define	ADC_SMPR_SMPSEL5_Msk (0x1UL << ADC_SMPR_SMPSEL5_Pos)

#define	ADC_SMPR_SMPSEL5 ADC_SMPR_SMPSEL5_Msk

#define	ADC_SMPR_SMPSEL6_Pos (14U)

#define	ADC_SMPR_SMPSEL6_Msk (0x1UL << ADC_SMPR_SMPSEL6_Pos)

#define	ADC_SMPR_SMPSEL6 ADC_SMPR_SMPSEL6_Msk

#define	ADC_SMPR_SMPSEL7_Pos (15U)

#define	ADC_SMPR_SMPSEL7_Msk (0x1UL << ADC_SMPR_SMPSEL7_Pos)

#define	ADC_SMPR_SMPSEL7 ADC_SMPR_SMPSEL7_Msk

#define	ADC_SMPR_SMPSEL8_Pos (16U)

#define	ADC_SMPR_SMPSEL8_Msk (0x1UL << ADC_SMPR_SMPSEL8_Pos)

#define	ADC_SMPR_SMPSEL8 ADC_SMPR_SMPSEL8_Msk

#define	ADC_SMPR_SMPSEL9_Pos (17U)

#define	ADC_SMPR_SMPSEL9_Msk (0x1UL << ADC_SMPR_SMPSEL9_Pos)

#define	ADC_SMPR_SMPSEL9 ADC_SMPR_SMPSEL9_Msk

#define	ADC_SMPR_SMPSEL10_Pos (18U)

#define	ADC_SMPR_SMPSEL10_Msk (0x1UL << ADC_SMPR_SMPSEL10_Pos)

#define	ADC_SMPR_SMPSEL10 ADC_SMPR_SMPSEL10_Msk

#define	ADC_SMPR_SMPSEL11_Pos (19U)

#define	ADC_SMPR_SMPSEL11_Msk (0x1UL << ADC_SMPR_SMPSEL11_Pos)

#define	ADC_SMPR_SMPSEL11 ADC_SMPR_SMPSEL11_Msk

#define	ADC_SMPR_SMPSEL12_Pos (20U)

#define	ADC_SMPR_SMPSEL12_Msk (0x1UL << ADC_SMPR_SMPSEL12_Pos)

#define	ADC_SMPR_SMPSEL12 ADC_SMPR_SMPSEL12_Msk

#define	ADC_SMPR_SMPSEL13_Pos (21U)

#define	ADC_SMPR_SMPSEL13_Msk (0x1UL << ADC_SMPR_SMPSEL13_Pos)

#define	ADC_SMPR_SMPSEL13 ADC_SMPR_SMPSEL13_Msk

#define	ADC_SMPR_SMPSEL14_Pos (22U)

#define	ADC_SMPR_SMPSEL14_Msk (0x1UL << ADC_SMPR_SMPSEL14_Pos)

#define	ADC_SMPR_SMPSEL14 ADC_SMPR_SMPSEL14_Msk

#define	ADC_SMPR_SMPSEL15_Pos (23U)

#define	ADC_SMPR_SMPSEL15_Msk (0x1UL << ADC_SMPR_SMPSEL15_Pos)

#define	ADC_SMPR_SMPSEL15 ADC_SMPR_SMPSEL15_Msk

#define	ADC_SMPR_SMPSEL16_Pos (24U)

#define	ADC_SMPR_SMPSEL16_Msk (0x1UL << ADC_SMPR_SMPSEL16_Pos)

#define	ADC_SMPR_SMPSEL16 ADC_SMPR_SMPSEL16_Msk

#define	ADC_SMPR_SMPSEL17_Pos (25U)

#define	ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos)

#define	ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk

#define	ADC_TR1_LT1_Pos (0U)

#define	ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos)

#define	ADC_TR1_LT1 ADC_TR1_LT1_Msk

#define	ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos)

#define	ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos)

#define	ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos)

#define	ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos)

#define	ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos)

#define	ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos)

#define	ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos)

#define	ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos)

#define	ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos)

#define	ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos)

#define	ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos)

#define	ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos)

#define	ADC_TR1_HT1_Pos (16U)

#define	ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos)

#define	ADC_TR1_HT1 ADC_TR1_HT1_Msk

#define	ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos)

#define	ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos)

#define	ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos)

#define	ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos)

#define	ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos)

#define	ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos)

#define	ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos)

#define	ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos)

#define	ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos)

#define	ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos)

#define	ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos)

#define	ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos)

#define	ADC_TR2_LT2_Pos (0U)

#define	ADC_TR2_LT2_Msk (0xFFFUL << ADC_TR2_LT2_Pos)

#define	ADC_TR2_LT2 ADC_TR2_LT2_Msk

#define	ADC_TR2_LT2_0 (0x001UL << ADC_TR2_LT2_Pos)

#define	ADC_TR2_LT2_1 (0x002UL << ADC_TR2_LT2_Pos)

#define	ADC_TR2_LT2_2 (0x004UL << ADC_TR2_LT2_Pos)

#define	ADC_TR2_LT2_3 (0x008UL << ADC_TR2_LT2_Pos)

#define	ADC_TR2_LT2_4 (0x010UL << ADC_TR2_LT2_Pos)

#define	ADC_TR2_LT2_5 (0x020UL << ADC_TR2_LT2_Pos)

#define	ADC_TR2_LT2_6 (0x040UL << ADC_TR2_LT2_Pos)

#define	ADC_TR2_LT2_7 (0x080UL << ADC_TR2_LT2_Pos)

#define	ADC_TR2_LT2_8 (0x100UL << ADC_TR2_LT2_Pos)

#define	ADC_TR2_LT2_9 (0x200UL << ADC_TR2_LT2_Pos)

#define	ADC_TR2_LT2_10 (0x400UL << ADC_TR2_LT2_Pos)

#define	ADC_TR2_LT2_11 (0x800UL << ADC_TR2_LT2_Pos)

#define	ADC_TR2_HT2_Pos (16U)

#define	ADC_TR2_HT2_Msk (0xFFFUL << ADC_TR2_HT2_Pos)

#define	ADC_TR2_HT2 ADC_TR2_HT2_Msk

#define	ADC_TR2_HT2_0 (0x001UL << ADC_TR2_HT2_Pos)

#define	ADC_TR2_HT2_1 (0x002UL << ADC_TR2_HT2_Pos)

#define	ADC_TR2_HT2_2 (0x004UL << ADC_TR2_HT2_Pos)

#define	ADC_TR2_HT2_3 (0x008UL << ADC_TR2_HT2_Pos)

#define	ADC_TR2_HT2_4 (0x010UL << ADC_TR2_HT2_Pos)

#define	ADC_TR2_HT2_5 (0x020UL << ADC_TR2_HT2_Pos)

#define	ADC_TR2_HT2_6 (0x040UL << ADC_TR2_HT2_Pos)

#define	ADC_TR2_HT2_7 (0x080UL << ADC_TR2_HT2_Pos)

#define	ADC_TR2_HT2_8 (0x100UL << ADC_TR2_HT2_Pos)

#define	ADC_TR2_HT2_9 (0x200UL << ADC_TR2_HT2_Pos)

#define	ADC_TR2_HT2_10 (0x400UL << ADC_TR2_HT2_Pos)

#define	ADC_TR2_HT2_11 (0x800UL << ADC_TR2_HT2_Pos)

#define	ADC_CHSELR_CHSEL_Pos (0U)

#define	ADC_CHSELR_CHSEL_Msk (0x3FFFFUL << ADC_CHSELR_CHSEL_Pos)

#define	ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk

#define	ADC_CHSELR_CHSEL17_Pos (17U)

#define	ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos)

#define	ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk

#define	ADC_CHSELR_CHSEL16_Pos (16U)

#define	ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos)

#define	ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk

#define	ADC_CHSELR_CHSEL15_Pos (15U)

#define	ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos)

#define	ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk

#define	ADC_CHSELR_CHSEL14_Pos (14U)

#define	ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos)

#define	ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk

#define	ADC_CHSELR_CHSEL13_Pos (13U)

#define	ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos)

#define	ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk

#define	ADC_CHSELR_CHSEL12_Pos (12U)

#define	ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos)

#define	ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk

#define	ADC_CHSELR_CHSEL11_Pos (11U)

#define	ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos)

#define	ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk

#define	ADC_CHSELR_CHSEL10_Pos (10U)

#define	ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos)

#define	ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk

#define	ADC_CHSELR_CHSEL9_Pos (9U)

#define	ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos)

#define	ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk

#define	ADC_CHSELR_CHSEL8_Pos (8U)

#define	ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos)

#define	ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk

#define	ADC_CHSELR_CHSEL7_Pos (7U)

#define	ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos)

#define	ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk

#define	ADC_CHSELR_CHSEL6_Pos (6U)

#define	ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos)

#define	ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk

#define	ADC_CHSELR_CHSEL5_Pos (5U)

#define	ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos)

#define	ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk

#define	ADC_CHSELR_CHSEL4_Pos (4U)

#define	ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos)

#define	ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk

#define	ADC_CHSELR_CHSEL3_Pos (3U)

#define	ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos)

#define	ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk

#define	ADC_CHSELR_CHSEL2_Pos (2U)

#define	ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos)

#define	ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk

#define	ADC_CHSELR_CHSEL1_Pos (1U)

#define	ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos)

#define	ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk

#define	ADC_CHSELR_CHSEL0_Pos (0U)

#define	ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos)

#define	ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk

#define	ADC_CHSELR_SQ_ALL_Pos (0U)

#define	ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos)

#define	ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk

#define	ADC_CHSELR_SQ8_Pos (28U)

#define	ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos)

#define	ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk

#define	ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos)

#define	ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos)

#define	ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos)

#define	ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos)

#define	ADC_CHSELR_SQ7_Pos (24U)

#define	ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos)

#define	ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk

#define	ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos)

#define	ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos)

#define	ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos)

#define	ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos)

#define	ADC_CHSELR_SQ6_Pos (20U)

#define	ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos)

#define	ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk

#define	ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos)

#define	ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos)

#define	ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos)

#define	ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos)

#define	ADC_CHSELR_SQ5_Pos (16U)

#define	ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos)

#define	ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk

#define	ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos)

#define	ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos)

#define	ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos)

#define	ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos)

#define	ADC_CHSELR_SQ4_Pos (12U)

#define	ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos)

#define	ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk

#define	ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos)

#define	ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos)

#define	ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos)

#define	ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos)

#define	ADC_CHSELR_SQ3_Pos (8U)

#define	ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos)

#define	ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk

#define	ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos)

#define	ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos)

#define	ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos)

#define	ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos)

#define	ADC_CHSELR_SQ2_Pos (4U)

#define	ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos)

#define	ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk

#define	ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos)

#define	ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos)

#define	ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos)

#define	ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos)

#define	ADC_CHSELR_SQ1_Pos (0U)

#define	ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos)

#define	ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk

#define	ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos)

#define	ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos)

#define	ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos)

#define	ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos)

#define	ADC_TR3_LT3_Pos (0U)

#define	ADC_TR3_LT3_Msk (0xFFFUL << ADC_TR3_LT3_Pos)

#define	ADC_TR3_LT3 ADC_TR3_LT3_Msk

#define	ADC_TR3_LT3_0 (0x001UL << ADC_TR3_LT3_Pos)

#define	ADC_TR3_LT3_1 (0x002UL << ADC_TR3_LT3_Pos)

#define	ADC_TR3_LT3_2 (0x004UL << ADC_TR3_LT3_Pos)

#define	ADC_TR3_LT3_3 (0x008UL << ADC_TR3_LT3_Pos)

#define	ADC_TR3_LT3_4 (0x010UL << ADC_TR3_LT3_Pos)

#define	ADC_TR3_LT3_5 (0x020UL << ADC_TR3_LT3_Pos)

#define	ADC_TR3_LT3_6 (0x040UL << ADC_TR3_LT3_Pos)

#define	ADC_TR3_LT3_7 (0x080UL << ADC_TR3_LT3_Pos)

#define	ADC_TR3_LT3_8 (0x100UL << ADC_TR3_LT3_Pos)

#define	ADC_TR3_LT3_9 (0x200UL << ADC_TR3_LT3_Pos)

#define	ADC_TR3_LT3_10 (0x400UL << ADC_TR3_LT3_Pos)

#define	ADC_TR3_LT3_11 (0x800UL << ADC_TR3_LT3_Pos)

#define	ADC_TR3_HT3_Pos (16U)

#define	ADC_TR3_HT3_Msk (0xFFFUL << ADC_TR3_HT3_Pos)

#define	ADC_TR3_HT3 ADC_TR3_HT3_Msk

#define	ADC_TR3_HT3_0 (0x001UL << ADC_TR3_HT3_Pos)

#define	ADC_TR3_HT3_1 (0x002UL << ADC_TR3_HT3_Pos)

#define	ADC_TR3_HT3_2 (0x004UL << ADC_TR3_HT3_Pos)

#define	ADC_TR3_HT3_3 (0x008UL << ADC_TR3_HT3_Pos)

#define	ADC_TR3_HT3_4 (0x010UL << ADC_TR3_HT3_Pos)

#define	ADC_TR3_HT3_5 (0x020UL << ADC_TR3_HT3_Pos)

#define	ADC_TR3_HT3_6 (0x040UL << ADC_TR3_HT3_Pos)

#define	ADC_TR3_HT3_7 (0x080UL << ADC_TR3_HT3_Pos)

#define	ADC_TR3_HT3_8 (0x100UL << ADC_TR3_HT3_Pos)

#define	ADC_TR3_HT3_9 (0x200UL << ADC_TR3_HT3_Pos)

#define	ADC_TR3_HT3_10 (0x400UL << ADC_TR3_HT3_Pos)

#define	ADC_TR3_HT3_11 (0x800UL << ADC_TR3_HT3_Pos)

#define	ADC_DR_DATA_Pos (0U)

#define	ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos)

#define	ADC_DR_DATA ADC_DR_DATA_Msk

#define	ADC_DR_DATA_0 (0x0001UL << ADC_DR_DATA_Pos)

#define	ADC_DR_DATA_1 (0x0002UL << ADC_DR_DATA_Pos)

#define	ADC_DR_DATA_2 (0x0004UL << ADC_DR_DATA_Pos)

#define	ADC_DR_DATA_3 (0x0008UL << ADC_DR_DATA_Pos)

#define	ADC_DR_DATA_4 (0x0010UL << ADC_DR_DATA_Pos)

#define	ADC_DR_DATA_5 (0x0020UL << ADC_DR_DATA_Pos)

#define	ADC_DR_DATA_6 (0x0040UL << ADC_DR_DATA_Pos)

#define	ADC_DR_DATA_7 (0x0080UL << ADC_DR_DATA_Pos)

#define	ADC_DR_DATA_8 (0x0100UL << ADC_DR_DATA_Pos)

#define	ADC_DR_DATA_9 (0x0200UL << ADC_DR_DATA_Pos)

#define	ADC_DR_DATA_10 (0x0400UL << ADC_DR_DATA_Pos)

#define	ADC_DR_DATA_11 (0x0800UL << ADC_DR_DATA_Pos)

#define	ADC_DR_DATA_12 (0x1000UL << ADC_DR_DATA_Pos)

#define	ADC_DR_DATA_13 (0x2000UL << ADC_DR_DATA_Pos)

#define	ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos)

#define	ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos)

#define	ADC_AWD2CR_AWD2CH_Pos (0U)

#define	ADC_AWD2CR_AWD2CH_Msk (0x3FFFFUL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk

#define	ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD3CR_AWD3CH_Pos (0U)

#define	ADC_AWD3CR_AWD3CH_Msk (0x3FFFFUL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk

#define	ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_CALFACT_CALFACT_Pos (0U)

#define	ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos)

#define	ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk

#define	ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos)

#define	ADC_CALFACT_CALFACT_1 (0x02UL << ADC_CALFACT_CALFACT_Pos)

#define	ADC_CALFACT_CALFACT_2 (0x04UL << ADC_CALFACT_CALFACT_Pos)

#define	ADC_CALFACT_CALFACT_3 (0x08UL << ADC_CALFACT_CALFACT_Pos)

#define	ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos)

#define	ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos)

#define	ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos)

#define	ADC_CCR_PRESC_Pos (18U)

#define	ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos)

#define	ADC_CCR_PRESC ADC_CCR_PRESC_Msk

#define	ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos)

#define	ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos)

#define	ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos)

#define	ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos)

#define	ADC_CCR_VREFEN_Pos (22U)

#define	ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos)

#define	ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk

#define	ADC_CCR_TSEN_Pos (23U)

#define	ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos)

#define	ADC_CCR_TSEN ADC_CCR_TSEN_Msk

#define	ADC_CCR_VBATEN_Pos (24U)

#define	ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos)

#define	ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk

#define	COMP_CSR_EN_Pos (0U)

#define	COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos)

#define	COMP_CSR_EN COMP_CSR_EN_Msk

#define	COMP_CSR_PWRMODE_Pos (2U)

#define	COMP_CSR_PWRMODE_Msk (0x3UL << COMP_CSR_PWRMODE_Pos)

#define	COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk

#define	COMP_CSR_PWRMODE_0 (0x1UL << COMP_CSR_PWRMODE_Pos)

#define	COMP_CSR_PWRMODE_1 (0x2UL << COMP_CSR_PWRMODE_Pos)

#define	COMP_CSR_INMSEL_Pos (4U)

#define	COMP_CSR_INMSEL_Msk (0x7UL << COMP_CSR_INMSEL_Pos)

#define	COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk

#define	COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos)

#define	COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos)

#define	COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos)

#define	COMP_CSR_INPSEL_Pos (7U)

#define	COMP_CSR_INPSEL_Msk (0x3UL << COMP_CSR_INPSEL_Pos)

#define	COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk

#define	COMP_CSR_INPSEL_0 (0x1UL << COMP_CSR_INPSEL_Pos)

#define	COMP_CSR_INPSEL_1 (0x2UL << COMP_CSR_INPSEL_Pos)

#define	COMP_CSR_WINMODE_Pos (9U)

#define	COMP_CSR_WINMODE_Msk (0x1UL << COMP_CSR_WINMODE_Pos)

#define	COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk

#define	COMP_CSR_POLARITY_Pos (15U)

#define	COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos)

#define	COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk

#define	COMP_CSR_HYST_Pos (16U)

#define	COMP_CSR_HYST_Msk (0x3UL << COMP_CSR_HYST_Pos)

#define	COMP_CSR_HYST COMP_CSR_HYST_Msk

#define	COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos)

#define	COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos)

#define	COMP_CSR_BLANKING_Pos (18U)

#define	COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos)

#define	COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk

#define	COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos)

#define	COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos)

#define	COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos)

#define	COMP_CSR_BRGEN_Pos (22U)

#define	COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos)

#define	COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk

#define	COMP_CSR_SCALEN_Pos (23U)

#define	COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos)

#define	COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk

#define	COMP_CSR_INMESEL_Pos (25U)

#define	COMP_CSR_INMESEL_Msk (0x3UL << COMP_CSR_INMESEL_Pos)

#define	COMP_CSR_INMESEL COMP_CSR_INMESEL_Msk

#define	COMP_CSR_INMESEL_0 (0x1UL << COMP_CSR_INMESEL_Pos)

#define	COMP_CSR_INMESEL_1 (0x2UL << COMP_CSR_INMESEL_Pos)

#define	COMP_CSR_VALUE_Pos (30U)

#define	COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos)

#define	COMP_CSR_VALUE COMP_CSR_VALUE_Msk

#define	COMP_CSR_LOCK_Pos (31U)

#define	COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos)

#define	COMP_CSR_LOCK COMP_CSR_LOCK_Msk

#define	DAC_CR_EN1_Pos (0U)

#define	DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos)

#define	DAC_CR_EN1 DAC_CR_EN1_Msk

#define	DAC_CR_TEN1_Pos (1U)

#define	DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos)

#define	DAC_CR_TEN1 DAC_CR_TEN1_Msk

#define	DAC_CR_TSEL1_Pos (2U)

#define	DAC_CR_TSEL1_Msk (0xFUL << DAC_CR_TSEL1_Pos)

#define	DAC_CR_TSEL1 DAC_CR_TSEL1_Msk

#define	DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos)

#define	DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos)

#define	DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos)

#define	DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos)

#define	DAC_CR_WAVE1_Pos (6U)

#define	DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos)

#define	DAC_CR_WAVE1 DAC_CR_WAVE1_Msk

#define	DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos)

#define	DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos)

#define	DAC_CR_MAMP1_Pos (8U)

#define	DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos)

#define	DAC_CR_MAMP1 DAC_CR_MAMP1_Msk

#define	DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos)

#define	DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos)

#define	DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos)

#define	DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos)

#define	DAC_CR_DMAEN1_Pos (12U)

#define	DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos)

#define	DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk

#define	DAC_CR_DMAUDRIE1_Pos (13U)

#define	DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos)

#define	DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk

#define	DAC_CR_CEN1_Pos (14U)

#define	DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos)

#define	DAC_CR_CEN1 DAC_CR_CEN1_Msk

#define	DAC_SWTRIGR_SWTRIG1_Pos (0U)

#define	DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)

#define	DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk

#define	DAC_DHR12R1_DACC1DHR_Pos (0U)

#define	DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)

#define	DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk

#define	DAC_DHR12L1_DACC1DHR_Pos (4U)

#define	DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)

#define	DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk

#define	DAC_DHR8R1_DACC1DHR_Pos (0U)

#define	DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)

#define	DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk

#define	DAC_DHR12RD_DACC1DHR_Pos (0U)

#define	DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)

#define	DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk

#define	DAC_DHR12LD_DACC1DHR_Pos (4U)

#define	DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)

#define	DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk

#define	DAC_DHR8RD_DACC1DHR_Pos (0U)

#define	DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)

#define	DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk

#define	DAC_DOR1_DACC1DOR_Pos (0U)

#define	DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)

#define	DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk

#define	DAC_SR_DMAUDR1_Pos (13U)

#define	DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos)

#define	DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk

#define	DAC_SR_CAL_FLAG1_Pos (14U)

#define	DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos)

#define	DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk

#define	DAC_SR_BWST1_Pos (15U)

#define	DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos)

#define	DAC_SR_BWST1 DAC_SR_BWST1_Msk

#define	DAC_CCR_OTRIM1_Pos (0U)

#define	DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos)

#define	DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk

#define	DAC_MCR_MODE1_Pos (0U)

#define	DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos)

#define	DAC_MCR_MODE1 DAC_MCR_MODE1_Msk

#define	DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos)

#define	DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos)

#define	DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos)

#define	DAC_SHSR1_TSAMPLE1_Pos (0U)

#define	DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)

#define	DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk

#define	DAC_SHHR_THOLD1_Pos (0U)

#define	DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos)

#define	DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk

#define	DAC_SHRR_TREFRESH1_Pos (0U)

#define	DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos)

#define	DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk

#define	LPTIM_ISR_CMPM_Pos (0U)

#define	LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos)

#define	LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk

#define	LPTIM_ISR_ARRM_Pos (1U)

#define	LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos)

#define	LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk

#define	LPTIM_ISR_EXTTRIG_Pos (2U)

#define	LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos)

#define	LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk

#define	LPTIM_ISR_CMPOK_Pos (3U)

#define	LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos)

#define	LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk

#define	LPTIM_ISR_ARROK_Pos (4U)

#define	LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos)

#define	LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk

#define	LPTIM_ISR_UP_Pos (5U)

#define	LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos)

#define	LPTIM_ISR_UP LPTIM_ISR_UP_Msk

#define	LPTIM_ISR_DOWN_Pos (6U)

#define	LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos)

#define	LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk

#define	LPTIM_ISR_UE_Pos (7U)

#define	LPTIM_ISR_UE_Msk (0x1UL << LPTIM_ISR_UE_Pos)

#define	LPTIM_ISR_UE LPTIM_ISR_UE_Msk

#define	LPTIM_ISR_REPOK_Pos (8U)

#define	LPTIM_ISR_REPOK_Msk (0x1UL << LPTIM_ISR_REPOK_Pos)

#define	LPTIM_ISR_REPOK LPTIM_ISR_REPOK_Msk

#define	LPTIM_ICR_CMPMCF_Pos (0U)

#define	LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos)

#define	LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk

#define	LPTIM_ICR_ARRMCF_Pos (1U)

#define	LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos)

#define	LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk

#define	LPTIM_ICR_EXTTRIGCF_Pos (2U)

#define	LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)

#define	LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk

#define	LPTIM_ICR_CMPOKCF_Pos (3U)

#define	LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos)

#define	LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk

#define	LPTIM_ICR_ARROKCF_Pos (4U)

#define	LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos)

#define	LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk

#define	LPTIM_ICR_UPCF_Pos (5U)

#define	LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos)

#define	LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk

#define	LPTIM_ICR_DOWNCF_Pos (6U)

#define	LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos)

#define	LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk

#define	LPTIM_ICR_UECF_Pos (7U)

#define	LPTIM_ICR_UECF_Msk (0x1UL << LPTIM_ICR_UECF_Pos)

#define	LPTIM_ICR_UECF LPTIM_ICR_UECF_Msk

#define	LPTIM_ICR_REPOKCF_Pos (8U)

#define	LPTIM_ICR_REPOKCF_Msk (0x1UL << LPTIM_ICR_REPOKCF_Pos)

#define	LPTIM_ICR_REPOKCF LPTIM_ICR_REPOKCF_Msk

#define	LPTIM_IER_CMPMIE_Pos (0U)

#define	LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos)

#define	LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk

#define	LPTIM_IER_ARRMIE_Pos (1U)

#define	LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos)

#define	LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk

#define	LPTIM_IER_EXTTRIGIE_Pos (2U)

#define	LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)

#define	LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk

#define	LPTIM_IER_CMPOKIE_Pos (3U)

#define	LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos)

#define	LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk

#define	LPTIM_IER_ARROKIE_Pos (4U)

#define	LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos)

#define	LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk

#define	LPTIM_IER_UPIE_Pos (5U)

#define	LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos)

#define	LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk

#define	LPTIM_IER_DOWNIE_Pos (6U)

#define	LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos)

#define	LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk

#define	LPTIM_IER_UEIE_Pos (7U)

#define	LPTIM_IER_UEIE_Msk (0x1UL << LPTIM_IER_UEIE_Pos)

#define	LPTIM_IER_UEIE LPTIM_IER_UEIE_Msk

#define	LPTIM_IER_REPOKIE_Pos (8U)

#define	LPTIM_IER_REPOKIE_Msk (0x1UL << LPTIM_IER_REPOKIE_Pos)

#define	LPTIM_IER_REPOKIE LPTIM_IER_REPOKIE_Msk

#define	LPTIM_CFGR_CKSEL_Pos (0U)

#define	LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos)

#define	LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk

#define	LPTIM_CFGR_CKPOL_Pos (1U)

#define	LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos)

#define	LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk

#define	LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos)

#define	LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos)

#define	LPTIM_CFGR_CKFLT_Pos (3U)

#define	LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos)

#define	LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk

#define	LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos)

#define	LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos)

#define	LPTIM_CFGR_TRGFLT_Pos (6U)

#define	LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos)

#define	LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk

#define	LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos)

#define	LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos)

#define	LPTIM_CFGR_PRESC_Pos (9U)

#define	LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos)

#define	LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk

#define	LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos)

#define	LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos)

#define	LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos)

#define	LPTIM_CFGR_TRIGSEL_Pos (13U)

#define	LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)

#define	LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk

#define	LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)

#define	LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)

#define	LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)

#define	LPTIM_CFGR_TRIGEN_Pos (17U)

#define	LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos)

#define	LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk

#define	LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos)

#define	LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos)

#define	LPTIM_CFGR_TIMOUT_Pos (19U)

#define	LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos)

#define	LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk

#define	LPTIM_CFGR_WAVE_Pos (20U)

#define	LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos)

#define	LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk

#define	LPTIM_CFGR_WAVPOL_Pos (21U)

#define	LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos)

#define	LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk

#define	LPTIM_CFGR_PRELOAD_Pos (22U)

#define	LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos)

#define	LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk

#define	LPTIM_CFGR_COUNTMODE_Pos (23U)

#define	LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)

#define	LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk

#define	LPTIM_CFGR_ENC_Pos (24U)

#define	LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos)

#define	LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk

#define	LPTIM_CR_ENABLE_Pos (0U)

#define	LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos)

#define	LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk

#define	LPTIM_CR_SNGSTRT_Pos (1U)

#define	LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos)

#define	LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk

#define	LPTIM_CR_CNTSTRT_Pos (2U)

#define	LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos)

#define	LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk

#define	LPTIM_CR_COUNTRST_Pos (3U)

#define	LPTIM_CR_COUNTRST_Msk (0x1UL << LPTIM_CR_COUNTRST_Pos)

#define	LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk

#define	LPTIM_CR_RSTARE_Pos (4U)

#define	LPTIM_CR_RSTARE_Msk (0x1UL << LPTIM_CR_RSTARE_Pos)

#define	LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk

#define	LPTIM_CMP_CMP_Pos (0U)

#define	LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos)

#define	LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk

#define	LPTIM_ARR_ARR_Pos (0U)

#define	LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos)

#define	LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk

#define	LPTIM_CNT_CNT_Pos (0U)

#define	LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos)

#define	LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk

#define	LPTIM_OR_OR_Pos (0U)

#define	LPTIM_OR_OR_Msk (0x3UL << LPTIM_OR_OR_Pos)

#define	LPTIM_OR_OR LPTIM_OR_OR_Msk

#define	LPTIM_OR_OR_0 (0x1UL << LPTIM_OR_OR_Pos)

#define	LPTIM_OR_OR_1 (0x2UL << LPTIM_OR_OR_Pos)

#define	LPTIM_RCR_REP_Pos (0U)

#define	LPTIM_RCR_REP_Msk (0xFFUL << LPTIM_RCR_REP_Pos)

#define	LPTIM_RCR_REP LPTIM_RCR_REP_Msk

#define	USART_CR1_UE_Pos (0U)

#define	USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)

#define	USART_CR1_UE USART_CR1_UE_Msk

#define	USART_CR1_UESM_Pos (1U)

#define	USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos)

#define	USART_CR1_UESM USART_CR1_UESM_Msk

#define	USART_CR1_RE_Pos (2U)

#define	USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)

#define	USART_CR1_RE USART_CR1_RE_Msk

#define	USART_CR1_TE_Pos (3U)

#define	USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)

#define	USART_CR1_TE USART_CR1_TE_Msk

#define	USART_CR1_IDLEIE_Pos (4U)

#define	USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)

#define	USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk

#define	USART_CR1_RXNEIE_RXFNEIE_Pos (5U)

#define	USART_CR1_RXNEIE_RXFNEIE_Msk (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos)

#define	USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE_Msk

#define	USART_CR1_TCIE_Pos (6U)

#define	USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)

#define	USART_CR1_TCIE USART_CR1_TCIE_Msk

#define	USART_CR1_TXEIE_TXFNFIE_Pos (7U)

#define	USART_CR1_TXEIE_TXFNFIE_Msk (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos)

#define	USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE_Msk

#define	USART_CR1_PEIE_Pos (8U)

#define	USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)

#define	USART_CR1_PEIE USART_CR1_PEIE_Msk

#define	USART_CR1_PS_Pos (9U)

#define	USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)

#define	USART_CR1_PS USART_CR1_PS_Msk

#define	USART_CR1_PCE_Pos (10U)

#define	USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)

#define	USART_CR1_PCE USART_CR1_PCE_Msk

#define	USART_CR1_WAKE_Pos (11U)

#define	USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)

#define	USART_CR1_WAKE USART_CR1_WAKE_Msk

#define	USART_CR1_M_Pos (12U)

#define	USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos)

#define	USART_CR1_M USART_CR1_M_Msk

#define	USART_CR1_M0_Pos (12U)

#define	USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos)

#define	USART_CR1_M0 USART_CR1_M0_Msk

#define	USART_CR1_MME_Pos (13U)

#define	USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos)

#define	USART_CR1_MME USART_CR1_MME_Msk

#define	USART_CR1_CMIE_Pos (14U)

#define	USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos)

#define	USART_CR1_CMIE USART_CR1_CMIE_Msk

#define	USART_CR1_OVER8_Pos (15U)

#define	USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)

#define	USART_CR1_OVER8 USART_CR1_OVER8_Msk

#define	USART_CR1_DEDT_Pos (16U)

#define	USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos)

#define	USART_CR1_DEDT USART_CR1_DEDT_Msk

#define	USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos)

#define	USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos)

#define	USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos)

#define	USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos)

#define	USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos)

#define	USART_CR1_DEAT_Pos (21U)

#define	USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos)

#define	USART_CR1_DEAT USART_CR1_DEAT_Msk

#define	USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos)

#define	USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos)

#define	USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos)

#define	USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos)

#define	USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos)

#define	USART_CR1_RTOIE_Pos (26U)

#define	USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos)

#define	USART_CR1_RTOIE USART_CR1_RTOIE_Msk

#define	USART_CR1_EOBIE_Pos (27U)

#define	USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos)

#define	USART_CR1_EOBIE USART_CR1_EOBIE_Msk

#define	USART_CR1_M1_Pos (28U)

#define	USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos)

#define	USART_CR1_M1 USART_CR1_M1_Msk

#define	USART_CR1_FIFOEN_Pos (29U)

#define	USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos)

#define	USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk

#define	USART_CR1_TXFEIE_Pos (30U)

#define	USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos)

#define	USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk

#define	USART_CR1_RXFFIE_Pos (31U)

#define	USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos)

#define	USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk

#define	USART_CR2_SLVEN_Pos (0U)

#define	USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos)

#define	USART_CR2_SLVEN USART_CR2_SLVEN_Msk

#define	USART_CR2_DIS_NSS_Pos (3U)

#define	USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos)

#define	USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk

#define	USART_CR2_ADDM7_Pos (4U)

#define	USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos)

#define	USART_CR2_ADDM7 USART_CR2_ADDM7_Msk

#define	USART_CR2_LBDL_Pos (5U)

#define	USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)

#define	USART_CR2_LBDL USART_CR2_LBDL_Msk

#define	USART_CR2_LBDIE_Pos (6U)

#define	USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)

#define	USART_CR2_LBDIE USART_CR2_LBDIE_Msk

#define	USART_CR2_LBCL_Pos (8U)

#define	USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)

#define	USART_CR2_LBCL USART_CR2_LBCL_Msk

#define	USART_CR2_CPHA_Pos (9U)

#define	USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)

#define	USART_CR2_CPHA USART_CR2_CPHA_Msk

#define	USART_CR2_CPOL_Pos (10U)

#define	USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)

#define	USART_CR2_CPOL USART_CR2_CPOL_Msk

#define	USART_CR2_CLKEN_Pos (11U)

#define	USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)

#define	USART_CR2_CLKEN USART_CR2_CLKEN_Msk

#define	USART_CR2_STOP_Pos (12U)

#define	USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)

#define	USART_CR2_STOP USART_CR2_STOP_Msk

#define	USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)

#define	USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)

#define	USART_CR2_LINEN_Pos (14U)

#define	USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)

#define	USART_CR2_LINEN USART_CR2_LINEN_Msk

#define	USART_CR2_SWAP_Pos (15U)

#define	USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos)

#define	USART_CR2_SWAP USART_CR2_SWAP_Msk

#define	USART_CR2_RXINV_Pos (16U)

#define	USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos)

#define	USART_CR2_RXINV USART_CR2_RXINV_Msk

#define	USART_CR2_TXINV_Pos (17U)

#define	USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos)

#define	USART_CR2_TXINV USART_CR2_TXINV_Msk

#define	USART_CR2_DATAINV_Pos (18U)

#define	USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos)

#define	USART_CR2_DATAINV USART_CR2_DATAINV_Msk

#define	USART_CR2_MSBFIRST_Pos (19U)

#define	USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos)

#define	USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk

#define	USART_CR2_ABREN_Pos (20U)

#define	USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos)

#define	USART_CR2_ABREN USART_CR2_ABREN_Msk

#define	USART_CR2_ABRMODE_Pos (21U)

#define	USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos)

#define	USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk

#define	USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos)

#define	USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos)

#define	USART_CR2_RTOEN_Pos (23U)

#define	USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos)

#define	USART_CR2_RTOEN USART_CR2_RTOEN_Msk

#define	USART_CR2_ADD_Pos (24U)

#define	USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos)

#define	USART_CR2_ADD USART_CR2_ADD_Msk

#define	USART_CR3_EIE_Pos (0U)

#define	USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)

#define	USART_CR3_EIE USART_CR3_EIE_Msk

#define	USART_CR3_IREN_Pos (1U)

#define	USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)

#define	USART_CR3_IREN USART_CR3_IREN_Msk

#define	USART_CR3_IRLP_Pos (2U)

#define	USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)

#define	USART_CR3_IRLP USART_CR3_IRLP_Msk

#define	USART_CR3_HDSEL_Pos (3U)

#define	USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)

#define	USART_CR3_HDSEL USART_CR3_HDSEL_Msk

#define	USART_CR3_NACK_Pos (4U)

#define	USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)

#define	USART_CR3_NACK USART_CR3_NACK_Msk

#define	USART_CR3_SCEN_Pos (5U)

#define	USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)

#define	USART_CR3_SCEN USART_CR3_SCEN_Msk

#define	USART_CR3_DMAR_Pos (6U)

#define	USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)

#define	USART_CR3_DMAR USART_CR3_DMAR_Msk

#define	USART_CR3_DMAT_Pos (7U)

#define	USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)

#define	USART_CR3_DMAT USART_CR3_DMAT_Msk

#define	USART_CR3_RTSE_Pos (8U)

#define	USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)

#define	USART_CR3_RTSE USART_CR3_RTSE_Msk

#define	USART_CR3_CTSE_Pos (9U)

#define	USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)

#define	USART_CR3_CTSE USART_CR3_CTSE_Msk

#define	USART_CR3_CTSIE_Pos (10U)

#define	USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)

#define	USART_CR3_CTSIE USART_CR3_CTSIE_Msk

#define	USART_CR3_ONEBIT_Pos (11U)

#define	USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos)

#define	USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk

#define	USART_CR3_OVRDIS_Pos (12U)

#define	USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos)

#define	USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk

#define	USART_CR3_DDRE_Pos (13U)

#define	USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos)

#define	USART_CR3_DDRE USART_CR3_DDRE_Msk

#define	USART_CR3_DEM_Pos (14U)

#define	USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos)

#define	USART_CR3_DEM USART_CR3_DEM_Msk

#define	USART_CR3_DEP_Pos (15U)

#define	USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos)

#define	USART_CR3_DEP USART_CR3_DEP_Msk

#define	USART_CR3_SCARCNT_Pos (17U)

#define	USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos)

#define	USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk

#define	USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos)

#define	USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos)

#define	USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos)

#define	USART_CR3_WUS_Pos (20U)

#define	USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos)

#define	USART_CR3_WUS USART_CR3_WUS_Msk

#define	USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos)

#define	USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos)

#define	USART_CR3_WUFIE_Pos (22U)

#define	USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos)

#define	USART_CR3_WUFIE USART_CR3_WUFIE_Msk

#define	USART_CR3_TXFTIE_Pos (23U)

#define	USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos)

#define	USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk

#define	USART_CR3_TCBGTIE_Pos (24U)

#define	USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos)

#define	USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk

#define	USART_CR3_RXFTCFG_Pos (25U)

#define	USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos)

#define	USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk

#define	USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos)

#define	USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos)

#define	USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos)

#define	USART_CR3_RXFTIE_Pos (28U)

#define	USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos)

#define	USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk

#define	USART_CR3_TXFTCFG_Pos (29U)

#define	USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos)

#define	USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk

#define	USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos)

#define	USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos)

#define	USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos)

#define	USART_BRR_BRR ((uint16_t)0xFFFF)

#define	USART_GTPR_PSC_Pos (0U)

#define	USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)

#define	USART_GTPR_PSC USART_GTPR_PSC_Msk

#define	USART_GTPR_GT_Pos (8U)

#define	USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)

#define	USART_GTPR_GT USART_GTPR_GT_Msk

#define	USART_RTOR_RTO_Pos (0U)

#define	USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos)

#define	USART_RTOR_RTO USART_RTOR_RTO_Msk

#define	USART_RTOR_BLEN_Pos (24U)

#define	USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos)

#define	USART_RTOR_BLEN USART_RTOR_BLEN_Msk

#define	USART_RQR_ABRRQ ((uint16_t)0x0001)

#define	USART_RQR_SBKRQ ((uint16_t)0x0002)

#define	USART_RQR_MMRQ ((uint16_t)0x0004)

#define	USART_RQR_RXFRQ ((uint16_t)0x0008)

#define	USART_RQR_TXFRQ ((uint16_t)0x0010)

#define	USART_ISR_PE_Pos (0U)

#define	USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos)

#define	USART_ISR_PE USART_ISR_PE_Msk

#define	USART_ISR_FE_Pos (1U)

#define	USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos)

#define	USART_ISR_FE USART_ISR_FE_Msk

#define	USART_ISR_NE_Pos (2U)

#define	USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos)

#define	USART_ISR_NE USART_ISR_NE_Msk

#define	USART_ISR_ORE_Pos (3U)

#define	USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos)

#define	USART_ISR_ORE USART_ISR_ORE_Msk

#define	USART_ISR_IDLE_Pos (4U)

#define	USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos)

#define	USART_ISR_IDLE USART_ISR_IDLE_Msk

#define	USART_ISR_RXNE_RXFNE_Pos (5U)

#define	USART_ISR_RXNE_RXFNE_Msk (0x1UL << USART_ISR_RXNE_RXFNE_Pos)

#define	USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE_Msk

#define	USART_ISR_TC_Pos (6U)

#define	USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos)

#define	USART_ISR_TC USART_ISR_TC_Msk

#define	USART_ISR_TXE_TXFNF_Pos (7U)

#define	USART_ISR_TXE_TXFNF_Msk (0x1UL << USART_ISR_TXE_TXFNF_Pos)

#define	USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF_Msk

#define	USART_ISR_LBDF_Pos (8U)

#define	USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos)

#define	USART_ISR_LBDF USART_ISR_LBDF_Msk

#define	USART_ISR_CTSIF_Pos (9U)

#define	USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos)

#define	USART_ISR_CTSIF USART_ISR_CTSIF_Msk

#define	USART_ISR_CTS_Pos (10U)

#define	USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos)

#define	USART_ISR_CTS USART_ISR_CTS_Msk

#define	USART_ISR_RTOF_Pos (11U)

#define	USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos)

#define	USART_ISR_RTOF USART_ISR_RTOF_Msk

#define	USART_ISR_EOBF_Pos (12U)

#define	USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos)

#define	USART_ISR_EOBF USART_ISR_EOBF_Msk

#define	USART_ISR_UDR_Pos (13U)

#define	USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos)

#define	USART_ISR_UDR USART_ISR_UDR_Msk

#define	USART_ISR_ABRE_Pos (14U)

#define	USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos)

#define	USART_ISR_ABRE USART_ISR_ABRE_Msk

#define	USART_ISR_ABRF_Pos (15U)

#define	USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos)

#define	USART_ISR_ABRF USART_ISR_ABRF_Msk

#define	USART_ISR_BUSY_Pos (16U)

#define	USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos)

#define	USART_ISR_BUSY USART_ISR_BUSY_Msk

#define	USART_ISR_CMF_Pos (17U)

#define	USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos)

#define	USART_ISR_CMF USART_ISR_CMF_Msk

#define	USART_ISR_SBKF_Pos (18U)

#define	USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos)

#define	USART_ISR_SBKF USART_ISR_SBKF_Msk

#define	USART_ISR_RWU_Pos (19U)

#define	USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos)

#define	USART_ISR_RWU USART_ISR_RWU_Msk

#define	USART_ISR_WUF_Pos (20U)

#define	USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos)

#define	USART_ISR_WUF USART_ISR_WUF_Msk

#define	USART_ISR_TEACK_Pos (21U)

#define	USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos)

#define	USART_ISR_TEACK USART_ISR_TEACK_Msk

#define	USART_ISR_REACK_Pos (22U)

#define	USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos)

#define	USART_ISR_REACK USART_ISR_REACK_Msk

#define	USART_ISR_TXFE_Pos (23U)

#define	USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos)

#define	USART_ISR_TXFE USART_ISR_TXFE_Msk

#define	USART_ISR_RXFF_Pos (24U)

#define	USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos)

#define	USART_ISR_RXFF USART_ISR_RXFF_Msk

#define	USART_ISR_TCBGT_Pos (25U)

#define	USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos)

#define	USART_ISR_TCBGT USART_ISR_TCBGT_Msk

#define	USART_ISR_RXFT_Pos (26U)

#define	USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos)

#define	USART_ISR_RXFT USART_ISR_RXFT_Msk

#define	USART_ISR_TXFT_Pos (27U)

#define	USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos)

#define	USART_ISR_TXFT USART_ISR_TXFT_Msk

#define	USART_ICR_PECF_Pos (0U)

#define	USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos)

#define	USART_ICR_PECF USART_ICR_PECF_Msk

#define	USART_ICR_FECF_Pos (1U)

#define	USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos)

#define	USART_ICR_FECF USART_ICR_FECF_Msk

#define	USART_ICR_NECF_Pos (2U)

#define	USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos)

#define	USART_ICR_NECF USART_ICR_NECF_Msk

#define	USART_ICR_ORECF_Pos (3U)

#define	USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos)

#define	USART_ICR_ORECF USART_ICR_ORECF_Msk

#define	USART_ICR_IDLECF_Pos (4U)

#define	USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos)

#define	USART_ICR_IDLECF USART_ICR_IDLECF_Msk

#define	USART_ICR_TXFECF_Pos (5U)

#define	USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos)

#define	USART_ICR_TXFECF USART_ICR_TXFECF_Msk

#define	USART_ICR_TCCF_Pos (6U)

#define	USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos)

#define	USART_ICR_TCCF USART_ICR_TCCF_Msk

#define	USART_ICR_TCBGTCF_Pos (7U)

#define	USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos)

#define	USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk

#define	USART_ICR_LBDCF_Pos (8U)

#define	USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos)

#define	USART_ICR_LBDCF USART_ICR_LBDCF_Msk

#define	USART_ICR_CTSCF_Pos (9U)

#define	USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos)

#define	USART_ICR_CTSCF USART_ICR_CTSCF_Msk

#define	USART_ICR_RTOCF_Pos (11U)

#define	USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos)

#define	USART_ICR_RTOCF USART_ICR_RTOCF_Msk

#define	USART_ICR_EOBCF_Pos (12U)

#define	USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos)

#define	USART_ICR_EOBCF USART_ICR_EOBCF_Msk

#define	USART_ICR_UDRCF_Pos (13U)

#define	USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos)

#define	USART_ICR_UDRCF USART_ICR_UDRCF_Msk

#define	USART_ICR_CMCF_Pos (17U)

#define	USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos)

#define	USART_ICR_CMCF USART_ICR_CMCF_Msk

#define	USART_ICR_WUCF_Pos (20U)

#define	USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos)

#define	USART_ICR_WUCF USART_ICR_WUCF_Msk

#define	USART_RDR_RDR_Pos (0U)

#define	USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos)

#define	USART_RDR_RDR USART_RDR_RDR_Msk

#define	USART_TDR_TDR_Pos (0U)

#define	USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos)

#define	USART_TDR_TDR USART_TDR_TDR_Msk

#define	USART_PRESC_PRESCALER_Pos (0U)

#define	USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos)

#define	USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk

#define	USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos)

#define	USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos)

#define	USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos)

#define	USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos)

#define	CRC_DR_DR_Pos (0U)

#define	CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)

#define	CRC_DR_DR CRC_DR_DR_Msk

#define	CRC_IDR_IDR_Pos (0U)

#define	CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)

#define	CRC_IDR_IDR CRC_IDR_IDR_Msk

#define	CRC_CR_RESET_Pos (0U)

#define	CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)

#define	CRC_CR_RESET CRC_CR_RESET_Msk

#define	CRC_CR_POLYSIZE_Pos (3U)

#define	CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos)

#define	CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk

#define	CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos)

#define	CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos)

#define	CRC_CR_REV_IN_Pos (5U)

#define	CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos)

#define	CRC_CR_REV_IN CRC_CR_REV_IN_Msk

#define	CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos)

#define	CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos)

#define	CRC_CR_REV_OUT_Pos (7U)

#define	CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos)

#define	CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk

#define	CRC_INIT_INIT_Pos (0U)

#define	CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)

#define	CRC_INIT_INIT CRC_INIT_INIT_Msk

#define	CRC_POL_POL_Pos (0U)

#define	CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos)

#define	CRC_POL_POL CRC_POL_POL_Msk

#define	AES_CR_EN_Pos (0U)

#define	AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos)

#define	AES_CR_EN AES_CR_EN_Msk

#define	AES_CR_DATATYPE_Pos (1U)

#define	AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos)

#define	AES_CR_DATATYPE AES_CR_DATATYPE_Msk

#define	AES_CR_DATATYPE_0 (0x1UL << AES_CR_DATATYPE_Pos)

#define	AES_CR_DATATYPE_1 (0x2UL << AES_CR_DATATYPE_Pos)

#define	AES_CR_MODE_Pos (3U)

#define	AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos)

#define	AES_CR_MODE AES_CR_MODE_Msk

#define	AES_CR_MODE_0 (0x1UL << AES_CR_MODE_Pos)

#define	AES_CR_MODE_1 (0x2UL << AES_CR_MODE_Pos)

#define	AES_CR_CHMOD_Pos (5U)

#define	AES_CR_CHMOD_Msk (0x803UL << AES_CR_CHMOD_Pos)

#define	AES_CR_CHMOD AES_CR_CHMOD_Msk

#define	AES_CR_CHMOD_0 (0x001UL << AES_CR_CHMOD_Pos)

#define	AES_CR_CHMOD_1 (0x002UL << AES_CR_CHMOD_Pos)

#define	AES_CR_CHMOD_2 (0x800UL << AES_CR_CHMOD_Pos)

#define	AES_CR_CCFC_Pos (7U)

#define	AES_CR_CCFC_Msk (0x1UL << AES_CR_CCFC_Pos)

#define	AES_CR_CCFC AES_CR_CCFC_Msk

#define	AES_CR_ERRC_Pos (8U)

#define	AES_CR_ERRC_Msk (0x1UL << AES_CR_ERRC_Pos)

#define	AES_CR_ERRC AES_CR_ERRC_Msk

#define	AES_CR_CCFIE_Pos (9U)

#define	AES_CR_CCFIE_Msk (0x1UL << AES_CR_CCFIE_Pos)

#define	AES_CR_CCFIE AES_CR_CCFIE_Msk

#define	AES_CR_ERRIE_Pos (10U)

#define	AES_CR_ERRIE_Msk (0x1UL << AES_CR_ERRIE_Pos)

#define	AES_CR_ERRIE AES_CR_ERRIE_Msk

#define	AES_CR_DMAINEN_Pos (11U)

#define	AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos)

#define	AES_CR_DMAINEN AES_CR_DMAINEN_Msk

#define	AES_CR_DMAOUTEN_Pos (12U)

#define	AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos)

#define	AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk

#define	AES_CR_GCMPH_Pos (13U)

#define	AES_CR_GCMPH_Msk (0x3UL << AES_CR_GCMPH_Pos)

#define	AES_CR_GCMPH AES_CR_GCMPH_Msk

#define	AES_CR_GCMPH_0 (0x1UL << AES_CR_GCMPH_Pos)

#define	AES_CR_GCMPH_1 (0x2UL << AES_CR_GCMPH_Pos)

#define	AES_CR_KEYSIZE_Pos (18U)

#define	AES_CR_KEYSIZE_Msk (0x1UL << AES_CR_KEYSIZE_Pos)

#define	AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk

#define	AES_CR_NPBLB_Pos (20U)

#define	AES_CR_NPBLB_Msk (0xFUL << AES_CR_NPBLB_Pos)

#define	AES_CR_NPBLB AES_CR_NPBLB_Msk

#define	AES_CR_NPBLB_0 (0x1UL << AES_CR_NPBLB_Pos)

#define	AES_CR_NPBLB_1 (0x2UL << AES_CR_NPBLB_Pos)

#define	AES_CR_NPBLB_2 (0x4UL << AES_CR_NPBLB_Pos)

#define	AES_CR_NPBLB_3 (0x8UL << AES_CR_NPBLB_Pos)

#define	AES_SR_CCF_Pos (0U)

#define	AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos)

#define	AES_SR_CCF AES_SR_CCF_Msk

#define	AES_SR_RDERR_Pos (1U)

#define	AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos)

#define	AES_SR_RDERR AES_SR_RDERR_Msk

#define	AES_SR_WRERR_Pos (2U)

#define	AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos)

#define	AES_SR_WRERR AES_SR_WRERR_Msk

#define	AES_SR_BUSY_Pos (3U)

#define	AES_SR_BUSY_Msk (0x1UL << AES_SR_BUSY_Pos)

#define	AES_SR_BUSY AES_SR_BUSY_Msk

#define	AES_DINR_Pos (0U)

#define	AES_DINR_Msk (0xFFFFFFFFUL << AES_DINR_Pos)

#define	AES_DINR AES_DINR_Msk

#define	AES_DOUTR_Pos (0U)

#define	AES_DOUTR_Msk (0xFFFFFFFFUL << AES_DOUTR_Pos)

#define	AES_DOUTR AES_DOUTR_Msk

#define	AES_KEYR0_Pos (0U)

#define	AES_KEYR0_Msk (0xFFFFFFFFUL << AES_KEYR0_Pos)

#define	AES_KEYR0 AES_KEYR0_Msk

#define	AES_KEYR1_Pos (0U)

#define	AES_KEYR1_Msk (0xFFFFFFFFUL << AES_KEYR1_Pos)

#define	AES_KEYR1 AES_KEYR1_Msk

#define	AES_KEYR2_Pos (0U)

#define	AES_KEYR2_Msk (0xFFFFFFFFUL << AES_KEYR2_Pos)

#define	AES_KEYR2 AES_KEYR2_Msk

#define	AES_KEYR3_Pos (0U)

#define	AES_KEYR3_Msk (0xFFFFFFFFUL << AES_KEYR3_Pos)

#define	AES_KEYR3 AES_KEYR3_Msk

#define	AES_KEYR4_Pos (0U)

#define	AES_KEYR4_Msk (0xFFFFFFFFUL << AES_KEYR4_Pos)

#define	AES_KEYR4 AES_KEYR4_Msk

#define	AES_KEYR5_Pos (0U)

#define	AES_KEYR5_Msk (0xFFFFFFFFUL << AES_KEYR5_Pos)

#define	AES_KEYR5 AES_KEYR5_Msk

#define	AES_KEYR6_Pos (0U)

#define	AES_KEYR6_Msk (0xFFFFFFFFUL << AES_KEYR6_Pos)

#define	AES_KEYR6 AES_KEYR6_Msk

#define	AES_KEYR7_Pos (0U)

#define	AES_KEYR7_Msk (0xFFFFFFFFUL << AES_KEYR7_Pos)

#define	AES_KEYR7 AES_KEYR7_Msk

#define	AES_IVR0_Pos (0U)

#define	AES_IVR0_Msk (0xFFFFFFFFUL << AES_IVR0_Pos)

#define	AES_IVR0 AES_IVR0_Msk

#define	AES_IVR1_Pos (0U)

#define	AES_IVR1_Msk (0xFFFFFFFFUL << AES_IVR1_Pos)

#define	AES_IVR1 AES_IVR1_Msk

#define	AES_IVR2_Pos (0U)

#define	AES_IVR2_Msk (0xFFFFFFFFUL << AES_IVR2_Pos)

#define	AES_IVR2 AES_IVR2_Msk

#define	AES_IVR3_Pos (0U)

#define	AES_IVR3_Msk (0xFFFFFFFFUL << AES_IVR3_Pos)

#define	AES_IVR3 AES_IVR3_Msk

#define	AES_SUSP0R_Pos (0U)

#define	AES_SUSP0R_Msk (0xFFFFFFFFUL << AES_SUSP0R_Pos)

#define	AES_SUSP0R AES_SUSP0R_Msk

#define	AES_SUSP1R_Pos (0U)

#define	AES_SUSP1R_Msk (0xFFFFFFFFUL << AES_SUSP1R_Pos)

#define	AES_SUSP1R AES_SUSP1R_Msk

#define	AES_SUSP2R_Pos (0U)

#define	AES_SUSP2R_Msk (0xFFFFFFFFUL << AES_SUSP2R_Pos)

#define	AES_SUSP2R AES_SUSP2R_Msk

#define	AES_SUSP3R_Pos (0U)

#define	AES_SUSP3R_Msk (0xFFFFFFFFUL << AES_SUSP3R_Pos)

#define	AES_SUSP3R AES_SUSP3R_Msk

#define	AES_SUSP4R_Pos (0U)

#define	AES_SUSP4R_Msk (0xFFFFFFFFUL << AES_SUSP4R_Pos)

#define	AES_SUSP4R AES_SUSP4R_Msk

#define	AES_SUSP5R_Pos (0U)

#define	AES_SUSP5R_Msk (0xFFFFFFFFUL << AES_SUSP5R_Pos)

#define	AES_SUSP5R AES_SUSP5R_Msk

#define	AES_SUSP6R_Pos (0U)

#define	AES_SUSP6R_Msk (0xFFFFFFFFUL << AES_SUSP6R_Pos)

#define	AES_SUSP6R AES_SUSP6R_Msk

#define	AES_SUSP7R_Pos (0U)

#define	AES_SUSP7R_Msk (0xFFFFFFFFUL << AES_SUSP7R_Pos)

#define	AES_SUSP7R AES_SUSP7R_Msk

#define	DMA_ISR_GIF1_Pos (0U)

#define	DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos)

#define	DMA_ISR_GIF1 DMA_ISR_GIF1_Msk

#define	DMA_ISR_TCIF1_Pos (1U)

#define	DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos)

#define	DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk

#define	DMA_ISR_HTIF1_Pos (2U)

#define	DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos)

#define	DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk

#define	DMA_ISR_TEIF1_Pos (3U)

#define	DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos)

#define	DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk

#define	DMA_ISR_GIF2_Pos (4U)

#define	DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos)

#define	DMA_ISR_GIF2 DMA_ISR_GIF2_Msk

#define	DMA_ISR_TCIF2_Pos (5U)

#define	DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos)

#define	DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk

#define	DMA_ISR_HTIF2_Pos (6U)

#define	DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos)

#define	DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk

#define	DMA_ISR_TEIF2_Pos (7U)

#define	DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos)

#define	DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk

#define	DMA_ISR_GIF3_Pos (8U)

#define	DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos)

#define	DMA_ISR_GIF3 DMA_ISR_GIF3_Msk

#define	DMA_ISR_TCIF3_Pos (9U)

#define	DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos)

#define	DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk

#define	DMA_ISR_HTIF3_Pos (10U)

#define	DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos)

#define	DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk

#define	DMA_ISR_TEIF3_Pos (11U)

#define	DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos)

#define	DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk

#define	DMA_ISR_GIF4_Pos (12U)

#define	DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos)

#define	DMA_ISR_GIF4 DMA_ISR_GIF4_Msk

#define	DMA_ISR_TCIF4_Pos (13U)

#define	DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos)

#define	DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk

#define	DMA_ISR_HTIF4_Pos (14U)

#define	DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos)

#define	DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk

#define	DMA_ISR_TEIF4_Pos (15U)

#define	DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos)

#define	DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk

#define	DMA_ISR_GIF5_Pos (16U)

#define	DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos)

#define	DMA_ISR_GIF5 DMA_ISR_GIF5_Msk

#define	DMA_ISR_TCIF5_Pos (17U)

#define	DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos)

#define	DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk

#define	DMA_ISR_HTIF5_Pos (18U)

#define	DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos)

#define	DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk

#define	DMA_ISR_TEIF5_Pos (19U)

#define	DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos)

#define	DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk

#define	DMA_ISR_GIF6_Pos (20U)

#define	DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos)

#define	DMA_ISR_GIF6 DMA_ISR_GIF6_Msk

#define	DMA_ISR_TCIF6_Pos (21U)

#define	DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos)

#define	DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk

#define	DMA_ISR_HTIF6_Pos (22U)

#define	DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos)

#define	DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk

#define	DMA_ISR_TEIF6_Pos (23U)

#define	DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos)

#define	DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk

#define	DMA_ISR_GIF7_Pos (24U)

#define	DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos)

#define	DMA_ISR_GIF7 DMA_ISR_GIF7_Msk

#define	DMA_ISR_TCIF7_Pos (25U)

#define	DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos)

#define	DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk

#define	DMA_ISR_HTIF7_Pos (26U)

#define	DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos)

#define	DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk

#define	DMA_ISR_TEIF7_Pos (27U)

#define	DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos)

#define	DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk

#define	DMA_IFCR_CGIF1_Pos (0U)

#define	DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos)

#define	DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk

#define	DMA_IFCR_CTCIF1_Pos (1U)

#define	DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos)

#define	DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk

#define	DMA_IFCR_CHTIF1_Pos (2U)

#define	DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos)

#define	DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk

#define	DMA_IFCR_CTEIF1_Pos (3U)

#define	DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos)

#define	DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk

#define	DMA_IFCR_CGIF2_Pos (4U)

#define	DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos)

#define	DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk

#define	DMA_IFCR_CTCIF2_Pos (5U)

#define	DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos)

#define	DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk

#define	DMA_IFCR_CHTIF2_Pos (6U)

#define	DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos)

#define	DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk

#define	DMA_IFCR_CTEIF2_Pos (7U)

#define	DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos)

#define	DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk

#define	DMA_IFCR_CGIF3_Pos (8U)

#define	DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos)

#define	DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk

#define	DMA_IFCR_CTCIF3_Pos (9U)

#define	DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos)

#define	DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk

#define	DMA_IFCR_CHTIF3_Pos (10U)

#define	DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos)

#define	DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk

#define	DMA_IFCR_CTEIF3_Pos (11U)

#define	DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos)

#define	DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk

#define	DMA_IFCR_CGIF4_Pos (12U)

#define	DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos)

#define	DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk

#define	DMA_IFCR_CTCIF4_Pos (13U)

#define	DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos)

#define	DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk

#define	DMA_IFCR_CHTIF4_Pos (14U)

#define	DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos)

#define	DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk

#define	DMA_IFCR_CTEIF4_Pos (15U)

#define	DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos)

#define	DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk

#define	DMA_IFCR_CGIF5_Pos (16U)

#define	DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos)

#define	DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk

#define	DMA_IFCR_CTCIF5_Pos (17U)

#define	DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos)

#define	DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk

#define	DMA_IFCR_CHTIF5_Pos (18U)

#define	DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos)

#define	DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk

#define	DMA_IFCR_CTEIF5_Pos (19U)

#define	DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos)

#define	DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk

#define	DMA_IFCR_CGIF6_Pos (20U)

#define	DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos)

#define	DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk

#define	DMA_IFCR_CTCIF6_Pos (21U)

#define	DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos)

#define	DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk

#define	DMA_IFCR_CHTIF6_Pos (22U)

#define	DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos)

#define	DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk

#define	DMA_IFCR_CTEIF6_Pos (23U)

#define	DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos)

#define	DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk

#define	DMA_IFCR_CGIF7_Pos (24U)

#define	DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos)

#define	DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk

#define	DMA_IFCR_CTCIF7_Pos (25U)

#define	DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos)

#define	DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk

#define	DMA_IFCR_CHTIF7_Pos (26U)

#define	DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos)

#define	DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk

#define	DMA_IFCR_CTEIF7_Pos (27U)

#define	DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos)

#define	DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk

#define	DMA_CCR_EN_Pos (0U)

#define	DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos)

#define	DMA_CCR_EN DMA_CCR_EN_Msk

#define	DMA_CCR_TCIE_Pos (1U)

#define	DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos)

#define	DMA_CCR_TCIE DMA_CCR_TCIE_Msk

#define	DMA_CCR_HTIE_Pos (2U)

#define	DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos)

#define	DMA_CCR_HTIE DMA_CCR_HTIE_Msk

#define	DMA_CCR_TEIE_Pos (3U)

#define	DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos)

#define	DMA_CCR_TEIE DMA_CCR_TEIE_Msk

#define	DMA_CCR_DIR_Pos (4U)

#define	DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos)

#define	DMA_CCR_DIR DMA_CCR_DIR_Msk

#define	DMA_CCR_CIRC_Pos (5U)

#define	DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos)

#define	DMA_CCR_CIRC DMA_CCR_CIRC_Msk

#define	DMA_CCR_PINC_Pos (6U)

#define	DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos)

#define	DMA_CCR_PINC DMA_CCR_PINC_Msk

#define	DMA_CCR_MINC_Pos (7U)

#define	DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos)

#define	DMA_CCR_MINC DMA_CCR_MINC_Msk

#define	DMA_CCR_PSIZE_Pos (8U)

#define	DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos)

#define	DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk

#define	DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos)

#define	DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos)

#define	DMA_CCR_MSIZE_Pos (10U)

#define	DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos)

#define	DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk

#define	DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos)

#define	DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos)

#define	DMA_CCR_PL_Pos (12U)

#define	DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos)

#define	DMA_CCR_PL DMA_CCR_PL_Msk

#define	DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos)

#define	DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos)

#define	DMA_CCR_MEM2MEM_Pos (14U)

#define	DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos)

#define	DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk

#define	DMA_CCR_SECM_Pos (17U)

#define	DMA_CCR_SECM_Msk (0x1UL << DMA_CCR_SECM_Pos)

#define	DMA_CCR_SECM DMA_CCR_SECM_Msk

#define	DMA_CCR_SSEC_Pos (18U)

#define	DMA_CCR_SSEC_Msk (0x1UL << DMA_CCR_SSEC_Pos)

#define	DMA_CCR_SSEC DMA_CCR_SSEC_Msk

#define	DMA_CCR_DSEC_Pos (19U)

#define	DMA_CCR_DSEC_Msk (0x1UL << DMA_CCR_DSEC_Pos)

#define	DMA_CCR_DSEC DMA_CCR_DSEC_Msk

#define	DMA_CCR_PRIV_Pos (20U)

#define	DMA_CCR_PRIV_Msk (0x1UL << DMA_CCR_PRIV_Pos)

#define	DMA_CCR_PRIV DMA_CCR_PRIV_Msk

#define	DMA_CNDTR_NDT_Pos (0U)

#define	DMA_CNDTR_NDT_Msk (0x3FFFFUL << DMA_CNDTR_NDT_Pos)

#define	DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk

#define	DMA_CPAR_PA_Pos (0U)

#define	DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)

#define	DMA_CPAR_PA DMA_CPAR_PA_Msk

#define	DMA_CMAR_MA_Pos (0U)

#define	DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)

#define	DMA_CMAR_MA DMA_CMAR_MA_Msk

#define	DMAMUX_CxCR_DMAREQ_ID_Pos (0U)

#define	DMAMUX_CxCR_DMAREQ_ID_Msk (0x7FUL << DMAMUX_CxCR_DMAREQ_ID_Pos

#define	DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk

#define	DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos

#define	DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos

#define	DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos

#define	DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos

#define	DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos

#define	DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos

#define	DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos

#define	DMAMUX_CxCR_SOIE_Pos (8U)

#define	DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos)

#define	DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk

#define	DMAMUX_CxCR_EGE_Pos (9U)

#define	DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos)

#define	DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk

#define	DMAMUX_CxCR_SE_Pos (16U)

#define	DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos)

#define	DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk

#define	DMAMUX_CxCR_SPOL_Pos (17U)

#define	DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos)

#define	DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk

#define	DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos)

#define	DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos)

#define	DMAMUX_CxCR_NBREQ_Pos (19U)

#define	DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos

#define	DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk

#define	DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos

#define	DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos

#define	DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos

#define	DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos

#define	DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos

#define	DMAMUX_CxCR_SYNC_ID_Pos (24U)

#define	DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos

#define	DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk

#define	DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos

#define	DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos

#define	DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos

#define	DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos

#define	DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos

#define	DMAMUX_CSR_SOF0_Pos (0U)

#define	DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos)

#define	DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk

#define	DMAMUX_CSR_SOF1_Pos (1U)

#define	DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos)

#define	DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk

#define	DMAMUX_CSR_SOF2_Pos (2U)

#define	DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos)

#define	DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk

#define	DMAMUX_CSR_SOF3_Pos (3U)

#define	DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos)

#define	DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk

#define	DMAMUX_CSR_SOF4_Pos (4U)

#define	DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos)

#define	DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk

#define	DMAMUX_CSR_SOF5_Pos (5U)

#define	DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos)

#define	DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk

#define	DMAMUX_CSR_SOF6_Pos (6U)

#define	DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos)

#define	DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk

#define	DMAMUX_CSR_SOF7_Pos (7U)

#define	DMAMUX_CSR_SOF7_Msk (0x1UL << DMAMUX_CSR_SOF7_Pos)

#define	DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk

#define	DMAMUX_CSR_SOF8_Pos (8U)

#define	DMAMUX_CSR_SOF8_Msk (0x1UL << DMAMUX_CSR_SOF8_Pos)

#define	DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk

#define	DMAMUX_CSR_SOF9_Pos (9U)

#define	DMAMUX_CSR_SOF9_Msk (0x1UL << DMAMUX_CSR_SOF9_Pos)

#define	DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk

#define	DMAMUX_CSR_SOF10_Pos (10U)

#define	DMAMUX_CSR_SOF10_Msk (0x1UL << DMAMUX_CSR_SOF10_Pos)

#define	DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk

#define	DMAMUX_CSR_SOF11_Pos (11U)

#define	DMAMUX_CSR_SOF11_Msk (0x1UL << DMAMUX_CSR_SOF11_Pos)

#define	DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk

#define	DMAMUX_CSR_SOF12_Pos (12U)

#define	DMAMUX_CSR_SOF12_Msk (0x1UL << DMAMUX_CSR_SOF12_Pos)

#define	DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12_Msk

#define	DMAMUX_CSR_SOF13_Pos (13U)

#define	DMAMUX_CSR_SOF13_Msk (0x1UL << DMAMUX_CSR_SOF13_Pos)

#define	DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13_Msk

#define	DMAMUX_CFR_CSOF0_Pos (0U)

#define	DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos)

#define	DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk

#define	DMAMUX_CFR_CSOF1_Pos (1U)

#define	DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos)

#define	DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk

#define	DMAMUX_CFR_CSOF2_Pos (2U)

#define	DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos)

#define	DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk

#define	DMAMUX_CFR_CSOF3_Pos (3U)

#define	DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos)

#define	DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk

#define	DMAMUX_CFR_CSOF4_Pos (4U)

#define	DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos)

#define	DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk

#define	DMAMUX_CFR_CSOF5_Pos (5U)

#define	DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos)

#define	DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk

#define	DMAMUX_CFR_CSOF6_Pos (6U)

#define	DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos)

#define	DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk

#define	DMAMUX_CFR_CSOF7_Pos (7U)

#define	DMAMUX_CFR_CSOF7_Msk (0x1UL << DMAMUX_CFR_CSOF7_Pos)

#define	DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk

#define	DMAMUX_CFR_CSOF8_Pos (8U)

#define	DMAMUX_CFR_CSOF8_Msk (0x1UL << DMAMUX_CFR_CSOF8_Pos)

#define	DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk

#define	DMAMUX_CFR_CSOF9_Pos (9U)

#define	DMAMUX_CFR_CSOF9_Msk (0x1UL << DMAMUX_CFR_CSOF9_Pos)

#define	DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk

#define	DMAMUX_CFR_CSOF10_Pos (10U)

#define	DMAMUX_CFR_CSOF10_Msk (0x1UL << DMAMUX_CFR_CSOF10_Pos

#define	DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk

#define	DMAMUX_CFR_CSOF11_Pos (11U)

#define	DMAMUX_CFR_CSOF11_Msk (0x1UL << DMAMUX_CFR_CSOF11_Pos

#define	DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk

#define	DMAMUX_CFR_CSOF12_Pos (12U)

#define	DMAMUX_CFR_CSOF12_Msk (0x1UL << DMAMUX_CFR_CSOF12_Pos

#define	DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12_Msk

#define	DMAMUX_CFR_CSOF13_Pos (13U)

#define	DMAMUX_CFR_CSOF13_Msk (0x1UL << DMAMUX_CFR_CSOF13_Pos

#define	DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13_Msk

#define	DMAMUX_RGxCR_SIG_ID_Pos (0U)

#define	DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos

#define	DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk

#define	DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos

#define	DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos

#define	DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos

#define	DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos

#define	DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos

#define	DMAMUX_RGxCR_OIE_Pos (8U)

#define	DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos)

#define	DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk

#define	DMAMUX_RGxCR_GE_Pos (16U)

#define	DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos)

#define	DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk

#define	DMAMUX_RGxCR_GPOL_Pos (17U)

#define	DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos

#define	DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk

#define	DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos

#define	DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos

#define	DMAMUX_RGxCR_GNBREQ_Pos (19U)

#define	DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos

#define	DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk

#define	DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos

#define	DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos

#define	DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos

#define	DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos

#define	DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos

#define	DMAMUX_RGSR_OF0_Pos (0U)

#define	DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos)

#define	DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk

#define	DMAMUX_RGSR_OF1_Pos (1U)

#define	DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos)

#define	DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk

#define	DMAMUX_RGSR_OF2_Pos (2U)

#define	DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos)

#define	DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk

#define	DMAMUX_RGSR_OF3_Pos (3U)

#define	DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos)

#define	DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk

#define	DMAMUX_RGCFR_COF0_Pos (0U)

#define	DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos

#define	DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk

#define	DMAMUX_RGCFR_COF1_Pos (1U)

#define	DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos

#define	DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk

#define	DMAMUX_RGCFR_COF2_Pos (2U)

#define	DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos

#define	DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk

#define	DMAMUX_RGCFR_COF3_Pos (3U)

#define	DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos

#define	DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk

#define	EXTI_RTSR1_RT0_Pos (0U)

#define	EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos)

#define	EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk

#define	EXTI_RTSR1_RT1_Pos (1U)

#define	EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos)

#define	EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk

#define	EXTI_RTSR1_RT2_Pos (2U)

#define	EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos)

#define	EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk

#define	EXTI_RTSR1_RT3_Pos (3U)

#define	EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos)

#define	EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk

#define	EXTI_RTSR1_RT4_Pos (4U)

#define	EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos)

#define	EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk

#define	EXTI_RTSR1_RT5_Pos (5U)

#define	EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos)

#define	EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk

#define	EXTI_RTSR1_RT6_Pos (6U)

#define	EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos)

#define	EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk

#define	EXTI_RTSR1_RT7_Pos (7U)

#define	EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos)

#define	EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk

#define	EXTI_RTSR1_RT8_Pos (8U)

#define	EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos)

#define	EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk

#define	EXTI_RTSR1_RT9_Pos (9U)

#define	EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos)

#define	EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk

#define	EXTI_RTSR1_RT10_Pos (10U)

#define	EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos)

#define	EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk

#define	EXTI_RTSR1_RT11_Pos (11U)

#define	EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos)

#define	EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk

#define	EXTI_RTSR1_RT12_Pos (12U)

#define	EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos)

#define	EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk

#define	EXTI_RTSR1_RT13_Pos (13U)

#define	EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos)

#define	EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk

#define	EXTI_RTSR1_RT14_Pos (14U)

#define	EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos)

#define	EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk

#define	EXTI_RTSR1_RT15_Pos (15U)

#define	EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos)

#define	EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk

#define	EXTI_RTSR1_RT16_Pos (16U)

#define	EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos)

#define	EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk

#define	EXTI_RTSR1_RT21_Pos (21U)

#define	EXTI_RTSR1_RT21_Msk (0x1UL << EXTI_RTSR1_RT21_Pos)

#define	EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk

#define	EXTI_RTSR1_RT22_Pos (22U)

#define	EXTI_RTSR1_RT22_Msk (0x1UL << EXTI_RTSR1_RT22_Pos)

#define	EXTI_RTSR1_RT22 EXTI_RTSR1_RT22_Msk

#define	EXTI_FTSR1_FT0_Pos (0U)

#define	EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos)

#define	EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk

#define	EXTI_FTSR1_FT1_Pos (1U)

#define	EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos)

#define	EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk

#define	EXTI_FTSR1_FT2_Pos (2U)

#define	EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos)

#define	EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk

#define	EXTI_FTSR1_FT3_Pos (3U)

#define	EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos)

#define	EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk

#define	EXTI_FTSR1_FT4_Pos (4U)

#define	EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos)

#define	EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk

#define	EXTI_FTSR1_FT5_Pos (5U)

#define	EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos)

#define	EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk

#define	EXTI_FTSR1_FT6_Pos (6U)

#define	EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos)

#define	EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk

#define	EXTI_FTSR1_FT7_Pos (7U)

#define	EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos)

#define	EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk

#define	EXTI_FTSR1_FT8_Pos (8U)

#define	EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos)

#define	EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk

#define	EXTI_FTSR1_FT9_Pos (9U)

#define	EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos)

#define	EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk

#define	EXTI_FTSR1_FT10_Pos (10U)

#define	EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos)

#define	EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk

#define	EXTI_FTSR1_FT11_Pos (11U)

#define	EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos)

#define	EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk

#define	EXTI_FTSR1_FT12_Pos (12U)

#define	EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos)

#define	EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk

#define	EXTI_FTSR1_FT13_Pos (13U)

#define	EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos)

#define	EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk

#define	EXTI_FTSR1_FT14_Pos (14U)

#define	EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos)

#define	EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk

#define	EXTI_FTSR1_FT15_Pos (15U)

#define	EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos)

#define	EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk

#define	EXTI_FTSR1_FT16_Pos (16U)

#define	EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos)

#define	EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk

#define	EXTI_FTSR1_FT21_Pos (21U)

#define	EXTI_FTSR1_FT21_Msk (0x1UL << EXTI_FTSR1_FT21_Pos)

#define	EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk

#define	EXTI_FTSR1_FT22_Pos (22U)

#define	EXTI_FTSR1_FT22_Msk (0x1UL << EXTI_FTSR1_FT22_Pos)

#define	EXTI_FTSR1_FT22 EXTI_FTSR1_FT22_Msk

#define	EXTI_SWIER1_SWI0_Pos (0U)

#define	EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos)

#define	EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk

#define	EXTI_SWIER1_SWI1_Pos (1U)

#define	EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos)

#define	EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk

#define	EXTI_SWIER1_SWI2_Pos (2U)

#define	EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos)

#define	EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk

#define	EXTI_SWIER1_SWI3_Pos (3U)

#define	EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos)

#define	EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk

#define	EXTI_SWIER1_SWI4_Pos (4U)

#define	EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos)

#define	EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk

#define	EXTI_SWIER1_SWI5_Pos (5U)

#define	EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos)

#define	EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk

#define	EXTI_SWIER1_SWI6_Pos (6U)

#define	EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos)

#define	EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk

#define	EXTI_SWIER1_SWI7_Pos (7U)

#define	EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos)

#define	EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk

#define	EXTI_SWIER1_SWI8_Pos (8U)

#define	EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos)

#define	EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk

#define	EXTI_SWIER1_SWI9_Pos (9U)

#define	EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos)

#define	EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk

#define	EXTI_SWIER1_SWI10_Pos (10U)

#define	EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos)

#define	EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk

#define	EXTI_SWIER1_SWI11_Pos (11U)

#define	EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos)

#define	EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk

#define	EXTI_SWIER1_SWI12_Pos (12U)

#define	EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos)

#define	EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk

#define	EXTI_SWIER1_SWI13_Pos (13U)

#define	EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos)

#define	EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk

#define	EXTI_SWIER1_SWI14_Pos (14U)

#define	EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos)

#define	EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk

#define	EXTI_SWIER1_SWI15_Pos (15U)

#define	EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos)

#define	EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk

#define	EXTI_SWIER1_SWI16_Pos (16U)

#define	EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos)

#define	EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk

#define	EXTI_SWIER1_SWI21_Pos (21U)

#define	EXTI_SWIER1_SWI21_Msk (0x1UL << EXTI_SWIER1_SWI21_Pos)

#define	EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk

#define	EXTI_SWIER1_SWI22_Pos (22U)

#define	EXTI_SWIER1_SWI22_Msk (0x1UL << EXTI_SWIER1_SWI22_Pos)

#define	EXTI_SWIER1_SWI22 EXTI_SWIER1_SWI22_Msk

#define	EXTI_PR1_PIF0_Pos (0U)

#define	EXTI_PR1_PIF0_Msk (0x1UL << EXTI_PR1_PIF0_Pos)

#define	EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk

#define	EXTI_PR1_PIF1_Pos (1U)

#define	EXTI_PR1_PIF1_Msk (0x1UL << EXTI_PR1_PIF1_Pos)

#define	EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk

#define	EXTI_PR1_PIF2_Pos (2U)

#define	EXTI_PR1_PIF2_Msk (0x1UL << EXTI_PR1_PIF2_Pos)

#define	EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk

#define	EXTI_PR1_PIF3_Pos (3U)

#define	EXTI_PR1_PIF3_Msk (0x1UL << EXTI_PR1_PIF3_Pos)

#define	EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk

#define	EXTI_PR1_PIF4_Pos (4U)

#define	EXTI_PR1_PIF4_Msk (0x1UL << EXTI_PR1_PIF4_Pos)

#define	EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk

#define	EXTI_PR1_PIF5_Pos (5U)

#define	EXTI_PR1_PIF5_Msk (0x1UL << EXTI_PR1_PIF5_Pos)

#define	EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk

#define	EXTI_PR1_PIF6_Pos (6U)

#define	EXTI_PR1_PIF6_Msk (0x1UL << EXTI_PR1_PIF6_Pos)

#define	EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk

#define	EXTI_PR1_PIF7_Pos (7U)

#define	EXTI_PR1_PIF7_Msk (0x1UL << EXTI_PR1_PIF7_Pos)

#define	EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk

#define	EXTI_PR1_PIF8_Pos (8U)

#define	EXTI_PR1_PIF8_Msk (0x1UL << EXTI_PR1_PIF8_Pos)

#define	EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk

#define	EXTI_PR1_PIF9_Pos (9U)

#define	EXTI_PR1_PIF9_Msk (0x1UL << EXTI_PR1_PIF9_Pos)

#define	EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk

#define	EXTI_PR1_PIF10_Pos (10U)

#define	EXTI_PR1_PIF10_Msk (0x1UL << EXTI_PR1_PIF10_Pos)

#define	EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk

#define	EXTI_PR1_PIF11_Pos (11U)

#define	EXTI_PR1_PIF11_Msk (0x1UL << EXTI_PR1_PIF11_Pos)

#define	EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk

#define	EXTI_PR1_PIF12_Pos (12U)

#define	EXTI_PR1_PIF12_Msk (0x1UL << EXTI_PR1_PIF12_Pos)

#define	EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk

#define	EXTI_PR1_PIF13_Pos (13U)

#define	EXTI_PR1_PIF13_Msk (0x1UL << EXTI_PR1_PIF13_Pos)

#define	EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk

#define	EXTI_PR1_PIF14_Pos (14U)

#define	EXTI_PR1_PIF14_Msk (0x1UL << EXTI_PR1_PIF14_Pos)

#define	EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk

#define	EXTI_PR1_PIF15_Pos (15U)

#define	EXTI_PR1_PIF15_Msk (0x1UL << EXTI_PR1_PIF15_Pos)

#define	EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk

#define	EXTI_PR1_PIF16_Pos (16U)

#define	EXTI_PR1_PIF16_Msk (0x1UL << EXTI_PR1_PIF16_Pos)

#define	EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk

#define	EXTI_PR1_PIF21_Pos (21U)

#define	EXTI_PR1_PIF21_Msk (0x1UL << EXTI_PR1_PIF21_Pos)

#define	EXTI_PR1_PIF21 EXTI_PR1_PIF21_Msk

#define	EXTI_PR1_PIF22_Pos (22U)

#define	EXTI_PR1_PIF22_Msk (0x1UL << EXTI_PR1_PIF22_Pos)

#define	EXTI_PR1_PIF22 EXTI_PR1_PIF22_Msk

#define	EXTI_RTSR2_RT34_Pos (2U)

#define	EXTI_RTSR2_RT34_Msk (0x1UL << EXTI_RTSR2_RT34_Pos)

#define	EXTI_RTSR2_RT34 EXTI_RTSR2_RT34_Msk

#define	EXTI_RTSR2_RT40_Pos (8U)

#define	EXTI_RTSR2_RT40_Msk (0x1UL << EXTI_RTSR2_RT40_Pos)

#define	EXTI_RTSR2_RT40 EXTI_RTSR2_RT40_Msk

#define	EXTI_RTSR2_RT41_Pos (9U)

#define	EXTI_RTSR2_RT41_Msk (0x1UL << EXTI_RTSR2_RT41_Pos)

#define	EXTI_RTSR2_RT41 EXTI_RTSR2_RT41_Msk

#define	EXTI_RTSR2_RT45_Pos (13U)

#define	EXTI_RTSR2_RT45_Msk (0x1UL << EXTI_RTSR2_RT45_Pos)

#define	EXTI_RTSR2_RT45 EXTI_RTSR2_RT45_Msk

#define	EXTI_FTSR2_FT34_Pos (2U)

#define	EXTI_FTSR2_FT34_Msk (0x1UL << EXTI_FTSR2_FT34_Pos)

#define	EXTI_FTSR2_FT34 EXTI_FTSR2_FT34_Msk

#define	EXTI_FTSR2_FT40_Pos (8U)

#define	EXTI_FTSR2_FT40_Msk (0x1UL << EXTI_FTSR2_FT40_Pos)

#define	EXTI_FTSR2_FT40 EXTI_FTSR2_FT40_Msk

#define	EXTI_FTSR2_FT41_Pos (9U)

#define	EXTI_FTSR2_FT41_Msk (0x1UL << EXTI_FTSR2_FT41_Pos)

#define	EXTI_FTSR2_FT41 EXTI_FTSR2_FT41_Msk

#define	EXTI_FTSR2_FT45_Pos (13U)

#define	EXTI_FTSR2_FT45_Msk (0x1UL << EXTI_FTSR2_FT45_Pos)

#define	EXTI_FTSR2_FT45 EXTI_FTSR2_FT45_Msk

#define	EXTI_SWIER2_SWI34_Pos (2U)

#define	EXTI_SWIER2_SWI34_Msk (0x1UL << EXTI_SWIER2_SWI34_Pos)

#define	EXTI_SWIER2_SWI34 EXTI_SWIER2_SWI34_Msk

#define	EXTI_SWIER2_SWI40_Pos (8U)

#define	EXTI_SWIER2_SWI40_Msk (0x1UL << EXTI_SWIER2_SWI40_Pos)

#define	EXTI_SWIER2_SWI40 EXTI_SWIER2_SWI40_Msk

#define	EXTI_SWIER2_SWI41_Pos (9U)

#define	EXTI_SWIER2_SWI41_Msk (0x1UL << EXTI_SWIER2_SWI41_Pos)

#define	EXTI_SWIER2_SWI41 EXTI_SWIER2_SWI41_Msk

#define	EXTI_SWIER2_SWI45_Pos (13U)

#define	EXTI_SWIER2_SWI45_Msk (0x1UL << EXTI_SWIER2_SWI45_Pos)

#define	EXTI_SWIER2_SWI45 EXTI_SWIER2_SWI45_Msk

#define	EXTI_PR2_PIF34_Pos (2U)

#define	EXTI_PR2_PIF34_Msk (0x1UL << EXTI_PR2_PIF34_Pos)

#define	EXTI_PR2_PIF34 EXTI_PR2_PIF34_Msk

#define	EXTI_PR2_PIF40_Pos (8U)

#define	EXTI_PR2_PIF40_Msk (0x1UL << EXTI_PR2_PIF40_Pos)

#define	EXTI_PR2_PIF40 EXTI_PR2_PIF40_Msk

#define	EXTI_PR2_PIF41_Pos (9U)

#define	EXTI_PR2_PIF41_Msk (0x1UL << EXTI_PR2_PIF41_Pos)

#define	EXTI_PR2_PIF41 EXTI_PR2_PIF41_Msk

#define	EXTI_PR2_PIF45_Pos (13U)

#define	EXTI_PR2_PIF45_Msk (0x1UL << EXTI_PR2_PIF45_Pos)

#define	EXTI_PR2_PIF45 EXTI_PR2_PIF45_Msk

#define	EXTI_IMR1_IM0_Pos (0U)

#define	EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos)

#define	EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk

#define	EXTI_IMR1_IM1_Pos (1U)

#define	EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos)

#define	EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk

#define	EXTI_IMR1_IM2_Pos (2U)

#define	EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos)

#define	EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk

#define	EXTI_IMR1_IM3_Pos (3U)

#define	EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos)

#define	EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk

#define	EXTI_IMR1_IM4_Pos (4U)

#define	EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos)

#define	EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk

#define	EXTI_IMR1_IM5_Pos (5U)

#define	EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos)

#define	EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk

#define	EXTI_IMR1_IM6_Pos (6U)

#define	EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos)

#define	EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk

#define	EXTI_IMR1_IM7_Pos (7U)

#define	EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos)

#define	EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk

#define	EXTI_IMR1_IM8_Pos (8U)

#define	EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos)

#define	EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk

#define	EXTI_IMR1_IM9_Pos (9U)

#define	EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos)

#define	EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk

#define	EXTI_IMR1_IM10_Pos (10U)

#define	EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos)

#define	EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk

#define	EXTI_IMR1_IM11_Pos (11U)

#define	EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos)

#define	EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk

#define	EXTI_IMR1_IM12_Pos (12U)

#define	EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos)

#define	EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk

#define	EXTI_IMR1_IM13_Pos (13U)

#define	EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos)

#define	EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk

#define	EXTI_IMR1_IM14_Pos (14U)

#define	EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos)

#define	EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk

#define	EXTI_IMR1_IM15_Pos (15U)

#define	EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos)

#define	EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk

#define	EXTI_IMR1_IM16_Pos (16U)

#define	EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos)

#define	EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk

#define	EXTI_IMR1_IM17_Pos (17U)

#define	EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos)

#define	EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk

#define	EXTI_IMR1_IM18_Pos (18U)

#define	EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos)

#define	EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk

#define	EXTI_IMR1_IM19_Pos (19U)

#define	EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos)

#define	EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk

#define	EXTI_IMR1_IM20_Pos (20U)

#define	EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos)

#define	EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk

#define	EXTI_IMR1_IM21_Pos (21U)

#define	EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos)

#define	EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk

#define	EXTI_IMR1_IM22_Pos (22U)

#define	EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos)

#define	EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk

#define	EXTI_IMR1_IM23_Pos (23U)

#define	EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos)

#define	EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk

#define	EXTI_IMR1_IM24_Pos (24U)

#define	EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos)

#define	EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk

#define	EXTI_IMR1_IM25_Pos (25U)

#define	EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos)

#define	EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk

#define	EXTI_IMR1_IM26_Pos (26U)

#define	EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos)

#define	EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk

#define	EXTI_IMR1_IM27_Pos (27U)

#define	EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos)

#define	EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk

#define	EXTI_IMR1_IM28_Pos (28U)

#define	EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos)

#define	EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk

#define	EXTI_IMR1_IM29_Pos (29U)

#define	EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos)

#define	EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk

#define	EXTI_IMR1_IM30_Pos (30U)

#define	EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos)

#define	EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk

#define	EXTI_IMR1_IM31_Pos (31U)

#define	EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos)

#define	EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk

#define	EXTI_EMR1_EM0_Pos (0U)

#define	EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos)

#define	EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk

#define	EXTI_EMR1_EM1_Pos (1U)

#define	EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos)

#define	EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk

#define	EXTI_EMR1_EM2_Pos (2U)

#define	EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos)

#define	EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk

#define	EXTI_EMR1_EM3_Pos (3U)

#define	EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos)

#define	EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk

#define	EXTI_EMR1_EM4_Pos (4U)

#define	EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos)

#define	EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk

#define	EXTI_EMR1_EM5_Pos (5U)

#define	EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos)

#define	EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk

#define	EXTI_EMR1_EM6_Pos (6U)

#define	EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos)

#define	EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk

#define	EXTI_EMR1_EM7_Pos (7U)

#define	EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos)

#define	EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk

#define	EXTI_EMR1_EM8_Pos (8U)

#define	EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos)

#define	EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk

#define	EXTI_EMR1_EM9_Pos (9U)

#define	EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos)

#define	EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk

#define	EXTI_EMR1_EM10_Pos (10U)

#define	EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos)

#define	EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk

#define	EXTI_EMR1_EM11_Pos (11U)

#define	EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos)

#define	EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk

#define	EXTI_EMR1_EM12_Pos (12U)

#define	EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos)

#define	EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk

#define	EXTI_EMR1_EM13_Pos (13U)

#define	EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos)

#define	EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk

#define	EXTI_EMR1_EM14_Pos (14U)

#define	EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos)

#define	EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk

#define	EXTI_EMR1_EM15_Pos (15U)

#define	EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos)

#define	EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk

#define	EXTI_EMR1_EM17_Pos (17U)

#define	EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos)

#define	EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk

#define	EXTI_EMR1_EM19_Pos (19U)

#define	EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos)

#define	EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk

#define	EXTI_EMR1_EM20_Pos (20U)

#define	EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos)

#define	EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk

#define	EXTI_EMR1_EM21_Pos (21U)

#define	EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos)

#define	EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk

#define	EXTI_EMR1_EM22_Pos (22U)

#define	EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos)

#define	EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk

#define	EXTI_IMR2_IM34_Pos (2U)

#define	EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos)

#define	EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk

#define	EXTI_IMR2_IM36_Pos (4U)

#define	EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos)

#define	EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk

#define	EXTI_IMR2_IM37_Pos (5U)

#define	EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos)

#define	EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk

#define	EXTI_IMR2_IM38_Pos (6U)

#define	EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos)

#define	EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk

#define	EXTI_IMR2_IM39_Pos (7U)

#define	EXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos)

#define	EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk

#define	EXTI_IMR2_IM40_Pos (8U)

#define	EXTI_IMR2_IM40_Msk (0x1UL << EXTI_IMR2_IM40_Pos)

#define	EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk

#define	EXTI_IMR2_IM41_Pos (9U)

#define	EXTI_IMR2_IM41_Msk (0x1UL << EXTI_IMR2_IM41_Pos)

#define	EXTI_IMR2_IM41 EXTI_IMR2_IM41_Msk

#define	EXTI_IMR2_IM42_Pos (10U)

#define	EXTI_IMR2_IM42_Msk (0x1UL << EXTI_IMR2_IM42_Pos)

#define	EXTI_IMR2_IM42 EXTI_IMR2_IM42_Msk

#define	EXTI_IMR2_IM43_Pos (11U)

#define	EXTI_IMR2_IM43_Msk (0x1UL << EXTI_IMR2_IM43_Pos)

#define	EXTI_IMR2_IM43 EXTI_IMR2_IM43_Msk

#define	EXTI_IMR2_IM44_Pos (12U)

#define	EXTI_IMR2_IM44_Msk (0x1UL << EXTI_IMR2_IM44_Pos)

#define	EXTI_IMR2_IM44 EXTI_IMR2_IM44_Msk

#define	EXTI_IMR2_IM45_Pos (13U)

#define	EXTI_IMR2_IM45_Msk (0x1UL << EXTI_IMR2_IM45_Pos)

#define	EXTI_IMR2_IM45 EXTI_IMR2_IM45_Msk

#define	EXTI_IMR2_IM46_Pos (14U)

#define	EXTI_IMR2_IM46_Msk (0x1UL << EXTI_IMR2_IM46_Pos)

#define	EXTI_IMR2_IM46 EXTI_IMR2_IM46_Msk

#define	EXTI_EMR2_EM40_Pos (8U)

#define	EXTI_EMR2_EM40_Msk (0x1UL << EXTI_EMR2_EM40_Pos)

#define	EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk

#define	EXTI_EMR2_EM41_Pos (9U)

#define	EXTI_EMR2_EM41_Msk (0x1UL << EXTI_EMR2_EM41_Pos)

#define	EXTI_EMR2_EM41 EXTI_EMR2_EM41_Msk

#define	EXTI_C2IMR1_IM0_Pos (0U)

#define	EXTI_C2IMR1_IM0_Msk (0x1UL << EXTI_C2IMR1_IM0_Pos)

#define	EXTI_C2IMR1_IM0 EXTI_C2IMR1_IM0_Msk

#define	EXTI_C2IMR1_IM1_Pos (1U)

#define	EXTI_C2IMR1_IM1_Msk (0x1UL << EXTI_C2IMR1_IM1_Pos)

#define	EXTI_C2IMR1_IM1 EXTI_C2IMR1_IM1_Msk

#define	EXTI_C2IMR1_IM2_Pos (2U)

#define	EXTI_C2IMR1_IM2_Msk (0x1UL << EXTI_C2IMR1_IM2_Pos)

#define	EXTI_C2IMR1_IM2 EXTI_C2IMR1_IM2_Msk

#define	EXTI_C2IMR1_IM3_Pos (3U)

#define	EXTI_C2IMR1_IM3_Msk (0x1UL << EXTI_C2IMR1_IM3_Pos)

#define	EXTI_C2IMR1_IM3 EXTI_C2IMR1_IM3_Msk

#define	EXTI_C2IMR1_IM4_Pos (4U)

#define	EXTI_C2IMR1_IM4_Msk (0x1UL << EXTI_C2IMR1_IM4_Pos)

#define	EXTI_C2IMR1_IM4 EXTI_C2IMR1_IM4_Msk

#define	EXTI_C2IMR1_IM5_Pos (5U)

#define	EXTI_C2IMR1_IM5_Msk (0x1UL << EXTI_C2IMR1_IM5_Pos)

#define	EXTI_C2IMR1_IM5 EXTI_C2IMR1_IM5_Msk

#define	EXTI_C2IMR1_IM6_Pos (6U)

#define	EXTI_C2IMR1_IM6_Msk (0x1UL << EXTI_C2IMR1_IM6_Pos)

#define	EXTI_C2IMR1_IM6 EXTI_C2IMR1_IM6_Msk

#define	EXTI_C2IMR1_IM7_Pos (7U)

#define	EXTI_C2IMR1_IM7_Msk (0x1UL << EXTI_C2IMR1_IM7_Pos)

#define	EXTI_C2IMR1_IM7 EXTI_C2IMR1_IM7_Msk

#define	EXTI_C2IMR1_IM8_Pos (8U)

#define	EXTI_C2IMR1_IM8_Msk (0x1UL << EXTI_C2IMR1_IM8_Pos)

#define	EXTI_C2IMR1_IM8 EXTI_C2IMR1_IM8_Msk

#define	EXTI_C2IMR1_IM9_Pos (9U)

#define	EXTI_C2IMR1_IM9_Msk (0x1UL << EXTI_C2IMR1_IM9_Pos)

#define	EXTI_C2IMR1_IM9 EXTI_C2IMR1_IM9_Msk

#define	EXTI_C2IMR1_IM10_Pos (10U)

#define	EXTI_C2IMR1_IM10_Msk (0x1UL << EXTI_C2IMR1_IM10_Pos)

#define	EXTI_C2IMR1_IM10 EXTI_C2IMR1_IM10_Msk

#define	EXTI_C2IMR1_IM11_Pos (11U)

#define	EXTI_C2IMR1_IM11_Msk (0x1UL << EXTI_C2IMR1_IM11_Pos)

#define	EXTI_C2IMR1_IM11 EXTI_C2IMR1_IM11_Msk

#define	EXTI_C2IMR1_IM12_Pos (12U)

#define	EXTI_C2IMR1_IM12_Msk (0x1UL << EXTI_C2IMR1_IM12_Pos)

#define	EXTI_C2IMR1_IM12 EXTI_C2IMR1_IM12_Msk

#define	EXTI_C2IMR1_IM13_Pos (13U)

#define	EXTI_C2IMR1_IM13_Msk (0x1UL << EXTI_C2IMR1_IM13_Pos)

#define	EXTI_C2IMR1_IM13 EXTI_C2IMR1_IM13_Msk

#define	EXTI_C2IMR1_IM14_Pos (14U)

#define	EXTI_C2IMR1_IM14_Msk (0x1UL << EXTI_C2IMR1_IM14_Pos)

#define	EXTI_C2IMR1_IM14 EXTI_C2IMR1_IM14_Msk

#define	EXTI_C2IMR1_IM15_Pos (15U)

#define	EXTI_C2IMR1_IM15_Msk (0x1UL << EXTI_C2IMR1_IM15_Pos)

#define	EXTI_C2IMR1_IM15 EXTI_C2IMR1_IM15_Msk

#define	EXTI_C2IMR1_IM16_Pos (16U)

#define	EXTI_C2IMR1_IM16_Msk (0x1UL << EXTI_C2IMR1_IM16_Pos)

#define	EXTI_C2IMR1_IM16 EXTI_C2IMR1_IM16_Msk

#define	EXTI_C2IMR1_IM17_Pos (17U)

#define	EXTI_C2IMR1_IM17_Msk (0x1UL << EXTI_C2IMR1_IM17_Pos)

#define	EXTI_C2IMR1_IM17 EXTI_C2IMR1_IM17_Msk

#define	EXTI_C2IMR1_IM18_Pos (18U)

#define	EXTI_C2IMR1_IM18_Msk (0x1UL << EXTI_C2IMR1_IM18_Pos)

#define	EXTI_C2IMR1_IM18 EXTI_C2IMR1_IM18_Msk

#define	EXTI_C2IMR1_IM19_Pos (19U)

#define	EXTI_C2IMR1_IM19_Msk (0x1UL << EXTI_C2IMR1_IM19_Pos)

#define	EXTI_C2IMR1_IM19 EXTI_C2IMR1_IM19_Msk

#define	EXTI_C2IMR1_IM20_Pos (20U)

#define	EXTI_C2IMR1_IM20_Msk (0x1UL << EXTI_C2IMR1_IM20_Pos)

#define	EXTI_C2IMR1_IM20 EXTI_C2IMR1_IM20_Msk

#define	EXTI_C2IMR1_IM21_Pos (21U)

#define	EXTI_C2IMR1_IM21_Msk (0x1UL << EXTI_C2IMR1_IM21_Pos)

#define	EXTI_C2IMR1_IM21 EXTI_C2IMR1_IM21_Msk

#define	EXTI_C2IMR1_IM22_Pos (22U)

#define	EXTI_C2IMR1_IM22_Msk (0x1UL << EXTI_C2IMR1_IM22_Pos)

#define	EXTI_C2IMR1_IM22 EXTI_C2IMR1_IM22_Msk

#define	EXTI_C2IMR1_IM23_Pos (23U)

#define	EXTI_C2IMR1_IM23_Msk (0x1UL << EXTI_C2IMR1_IM23_Pos)

#define	EXTI_C2IMR1_IM23 EXTI_C2IMR1_IM23_Msk

#define	EXTI_C2IMR1_IM24_Pos (24U)

#define	EXTI_C2IMR1_IM24_Msk (0x1UL << EXTI_C2IMR1_IM24_Pos)

#define	EXTI_C2IMR1_IM24 EXTI_C2IMR1_IM24_Msk

#define	EXTI_C2IMR1_IM25_Pos (25U)

#define	EXTI_C2IMR1_IM25_Msk (0x1UL << EXTI_C2IMR1_IM25_Pos)

#define	EXTI_C2IMR1_IM25 EXTI_C2IMR1_IM25_Msk

#define	EXTI_C2IMR1_IM26_Pos (26U)

#define	EXTI_C2IMR1_IM26_Msk (0x1UL << EXTI_C2IMR1_IM26_Pos)

#define	EXTI_C2IMR1_IM26 EXTI_C2IMR1_IM26_Msk

#define	EXTI_C2IMR1_IM27_Pos (27U)

#define	EXTI_C2IMR1_IM27_Msk (0x1UL << EXTI_C2IMR1_IM27_Pos)

#define	EXTI_C2IMR1_IM27 EXTI_C2IMR1_IM27_Msk

#define	EXTI_C2IMR1_IM28_Pos (28U)

#define	EXTI_C2IMR1_IM28_Msk (0x1UL << EXTI_C2IMR1_IM28_Pos)

#define	EXTI_C2IMR1_IM28 EXTI_C2IMR1_IM28_Msk

#define	EXTI_C2IMR1_IM29_Pos (29U)

#define	EXTI_C2IMR1_IM29_Msk (0x1UL << EXTI_C2IMR1_IM29_Pos)

#define	EXTI_C2IMR1_IM29 EXTI_C2IMR1_IM29_Msk

#define	EXTI_C2IMR1_IM30_Pos (30U)

#define	EXTI_C2IMR1_IM30_Msk (0x1UL << EXTI_C2IMR1_IM30_Pos)

#define	EXTI_C2IMR1_IM30 EXTI_C2IMR1_IM30_Msk

#define	EXTI_C2IMR1_IM31_Pos (31U)

#define	EXTI_C2IMR1_IM31_Msk (0x1UL << EXTI_C2IMR1_IM31_Pos)

#define	EXTI_C2IMR1_IM31 EXTI_C2IMR1_IM31_Msk

#define	EXTI_C2EMR1_EM0_Pos (0U)

#define	EXTI_C2EMR1_EM0_Msk (0x1UL << EXTI_C2EMR1_EM0_Pos)

#define	EXTI_C2EMR1_EM0 EXTI_C2EMR1_EM0_Msk

#define	EXTI_C2EMR1_EM1_Pos (1U)

#define	EXTI_C2EMR1_EM1_Msk (0x1UL << EXTI_C2EMR1_EM1_Pos)

#define	EXTI_C2EMR1_EM1 EXTI_C2EMR1_EM1_Msk

#define	EXTI_C2EMR1_EM2_Pos (2U)

#define	EXTI_C2EMR1_EM2_Msk (0x1UL << EXTI_C2EMR1_EM2_Pos)

#define	EXTI_C2EMR1_EM2 EXTI_C2EMR1_EM2_Msk

#define	EXTI_C2EMR1_EM3_Pos (3U)

#define	EXTI_C2EMR1_EM3_Msk (0x1UL << EXTI_C2EMR1_EM3_Pos)

#define	EXTI_C2EMR1_EM3 EXTI_C2EMR1_EM3_Msk

#define	EXTI_C2EMR1_EM4_Pos (4U)

#define	EXTI_C2EMR1_EM4_Msk (0x1UL << EXTI_C2EMR1_EM4_Pos)

#define	EXTI_C2EMR1_EM4 EXTI_C2EMR1_EM4_Msk

#define	EXTI_C2EMR1_EM5_Pos (5U)

#define	EXTI_C2EMR1_EM5_Msk (0x1UL << EXTI_C2EMR1_EM5_Pos)

#define	EXTI_C2EMR1_EM5 EXTI_C2EMR1_EM5_Msk

#define	EXTI_C2EMR1_EM6_Pos (6U)

#define	EXTI_C2EMR1_EM6_Msk (0x1UL << EXTI_C2EMR1_EM6_Pos)

#define	EXTI_C2EMR1_EM6 EXTI_C2EMR1_EM6_Msk

#define	EXTI_C2EMR1_EM7_Pos (7U)

#define	EXTI_C2EMR1_EM7_Msk (0x1UL << EXTI_C2EMR1_EM7_Pos)

#define	EXTI_C2EMR1_EM7 EXTI_C2EMR1_EM7_Msk

#define	EXTI_C2EMR1_EM8_Pos (8U)

#define	EXTI_C2EMR1_EM8_Msk (0x1UL << EXTI_C2EMR1_EM8_Pos)

#define	EXTI_C2EMR1_EM8 EXTI_C2EMR1_EM8_Msk

#define	EXTI_C2EMR1_EM9_Pos (9U)

#define	EXTI_C2EMR1_EM9_Msk (0x1UL << EXTI_C2EMR1_EM9_Pos)

#define	EXTI_C2EMR1_EM9 EXTI_C2EMR1_EM9_Msk

#define	EXTI_C2EMR1_EM10_Pos (10U)

#define	EXTI_C2EMR1_EM10_Msk (0x1UL << EXTI_C2EMR1_EM10_Pos)

#define	EXTI_C2EMR1_EM10 EXTI_C2EMR1_EM10_Msk

#define	EXTI_C2EMR1_EM11_Pos (11U)

#define	EXTI_C2EMR1_EM11_Msk (0x1UL << EXTI_C2EMR1_EM11_Pos)

#define	EXTI_C2EMR1_EM11 EXTI_C2EMR1_EM11_Msk

#define	EXTI_C2EMR1_EM12_Pos (12U)

#define	EXTI_C2EMR1_EM12_Msk (0x1UL << EXTI_C2EMR1_EM12_Pos)

#define	EXTI_C2EMR1_EM12 EXTI_C2EMR1_EM12_Msk

#define	EXTI_C2EMR1_EM13_Pos (13U)

#define	EXTI_C2EMR1_EM13_Msk (0x1UL << EXTI_C2EMR1_EM13_Pos)

#define	EXTI_C2EMR1_EM13 EXTI_C2EMR1_EM13_Msk

#define	EXTI_C2EMR1_EM14_Pos (14U)

#define	EXTI_C2EMR1_EM14_Msk (0x1UL << EXTI_C2EMR1_EM14_Pos)

#define	EXTI_C2EMR1_EM14 EXTI_C2EMR1_EM14_Msk

#define	EXTI_C2EMR1_EM15_Pos (15U)

#define	EXTI_C2EMR1_EM15_Msk (0x1UL << EXTI_C2EMR1_EM15_Pos)

#define	EXTI_C2EMR1_EM15 EXTI_C2EMR1_EM15_Msk

#define	EXTI_C2EMR1_EM17_Pos (17U)

#define	EXTI_C2EMR1_EM17_Msk (0x1UL << EXTI_C2EMR1_EM17_Pos)

#define	EXTI_C2EMR1_EM17 EXTI_C2EMR1_EM17_Msk

#define	EXTI_C2EMR1_EM19_Pos (19U)

#define	EXTI_C2EMR1_EM19_Msk (0x1UL << EXTI_C2EMR1_EM19_Pos)

#define	EXTI_C2EMR1_EM19 EXTI_C2EMR1_EM19_Msk

#define	EXTI_C2EMR1_EM20_Pos (20U)

#define	EXTI_C2EMR1_EM20_Msk (0x1UL << EXTI_C2EMR1_EM20_Pos)

#define	EXTI_C2EMR1_EM20 EXTI_C2EMR1_EM20_Msk

#define	EXTI_C2EMR1_EM21_Pos (21U)

#define	EXTI_C2EMR1_EM21_Msk (0x1UL << EXTI_C2EMR1_EM21_Pos)

#define	EXTI_C2EMR1_EM21 EXTI_C2EMR1_EM21_Msk

#define	EXTI_C2EMR1_EM22_Pos (22U)

#define	EXTI_C2EMR1_EM22_Msk (0x1UL << EXTI_C2EMR1_EM22_Pos)

#define	EXTI_C2EMR1_EM22 EXTI_C2EMR1_EM22_Msk

#define	EXTI_C2IMR2_IM34_Pos (2U)

#define	EXTI_C2IMR2_IM34_Msk (0x1UL << EXTI_C2IMR2_IM34_Pos)

#define	EXTI_C2IMR2_IM34 EXTI_C2IMR2_IM34_Msk

#define	EXTI_C2IMR2_IM36_Pos (4U)

#define	EXTI_C2IMR2_IM36_Msk (0x1UL << EXTI_C2IMR2_IM36_Pos)

#define	EXTI_C2IMR2_IM36 EXTI_C2IMR2_IM36_Msk

#define	EXTI_C2IMR2_IM37_Pos (5U)

#define	EXTI_C2IMR2_IM37_Msk (0x1UL << EXTI_C2IMR2_IM37_Pos)

#define	EXTI_C2IMR2_IM37 EXTI_C2IMR2_IM37_Msk

#define	EXTI_C2IMR2_IM38_Pos (6U)

#define	EXTI_C2IMR2_IM38_Msk (0x1UL << EXTI_C2IMR2_IM38_Pos)

#define	EXTI_C2IMR2_IM38 EXTI_C2IMR2_IM38_Msk

#define	EXTI_C2IMR2_IM39_Pos (7U)

#define	EXTI_C2IMR2_IM39_Msk (0x1UL << EXTI_C2IMR2_IM39_Pos)

#define	EXTI_C2IMR2_IM39 EXTI_C2IMR2_IM39_Msk

#define	EXTI_C2IMR2_IM40_Pos (8U)

#define	EXTI_C2IMR2_IM40_Msk (0x1UL << EXTI_C2IMR2_IM40_Pos)

#define	EXTI_C2IMR2_IM40 EXTI_C2IMR2_IM40_Msk

#define	EXTI_C2IMR2_IM41_Pos (9U)

#define	EXTI_C2IMR2_IM41_Msk (0x1UL << EXTI_C2IMR2_IM41_Pos)

#define	EXTI_C2IMR2_IM41 EXTI_C2IMR2_IM41_Msk

#define	EXTI_C2IMR2_IM42_Pos (10U)

#define	EXTI_C2IMR2_IM42_Msk (0x1UL << EXTI_C2IMR2_IM42_Pos)

#define	EXTI_C2IMR2_IM42 EXTI_C2IMR2_IM42_Msk

#define	EXTI_C2IMR2_IM43_Pos (11U)

#define	EXTI_C2IMR2_IM43_Msk (0x1UL << EXTI_C2IMR2_IM43_Pos)

#define	EXTI_C2IMR2_IM43 EXTI_C2IMR2_IM43_Msk

#define	EXTI_C2IMR2_IM44_Pos (12U)

#define	EXTI_C2IMR2_IM44_Msk (0x1UL << EXTI_C2IMR2_IM44_Pos)

#define	EXTI_C2IMR2_IM44 EXTI_C2IMR2_IM44_Msk

#define	EXTI_C2IMR2_IM45_Pos (13U)

#define	EXTI_C2IMR2_IM45_Msk (0x1UL << EXTI_C2IMR2_IM45_Pos)

#define	EXTI_C2IMR2_IM45 EXTI_C2IMR2_IM45_Msk

#define	EXTI_C2IMR2_IM46_Pos (14U)

#define	EXTI_C2IMR2_IM46_Msk (0x1UL << EXTI_C2IMR2_IM46_Pos)

#define	EXTI_C2IMR2_IM46 EXTI_C2IMR2_IM46_Msk

#define	EXTI_C2EMR2_EM40_Pos (8U)

#define	EXTI_C2EMR2_EM40_Msk (0x1UL << EXTI_C2EMR2_EM40_Pos)

#define	EXTI_C2EMR2_EM40 EXTI_C2EMR2_EM40_Msk

#define	EXTI_C2EMR2_EM41_Pos (9U)

#define	EXTI_C2EMR2_EM41_Msk (0x1UL << EXTI_C2EMR2_EM41_Pos)

#define	EXTI_C2EMR2_EM41 EXTI_C2EMR2_EM41_Msk

#define	GTZC_CFGR1_TZIC_Pos (0U)

#define	GTZC_CFGR1_TZIC_Msk (0x01UL << GTZC_CFGR1_TZIC_Pos)

#define	GTZC_CFGR1_TZSC_Pos (1U)

#define	GTZC_CFGR1_TZSC_Msk (0x01UL << GTZC_CFGR1_TZSC_Pos)

#define	GTZC_CFGR1_AES_Pos (2U)

#define	GTZC_CFGR1_AES_Msk (0x01UL << GTZC_CFGR1_AES_Pos)

#define	GTZC_CFGR1_RNG_Pos (3U)

#define	GTZC_CFGR1_RNG_Msk (0x01UL << GTZC_CFGR1_RNG_Pos)

#define	GTZC_CFGR1_SUBGHZSPI_Pos (4U)

#define	GTZC_CFGR1_SUBGHZSPI_Msk (0x01UL << GTZC_CFGR1_SUBGHZSPI_Pos

#define	GTZC_CFGR1_PWR_Pos (5U)

#define	GTZC_CFGR1_PWR_Msk (0x01UL << GTZC_CFGR1_PWR_Pos)

#define	GTZC_CFGR1_FLASHIF_Pos (6U)

#define	GTZC_CFGR1_FLASHIF_Msk (0x01UL << GTZC_CFGR1_FLASHIF_Pos)

#define	GTZC_CFGR1_DMA1_Pos (7U)

#define	GTZC_CFGR1_DMA1_Msk (0x01UL << GTZC_CFGR1_DMA1_Pos)

#define	GTZC_CFGR1_DMA2_Pos (8U)

#define	GTZC_CFGR1_DMA2_Msk (0x01UL << GTZC_CFGR1_DMA2_Pos)

#define	GTZC_CFGR1_DMAMUX_Pos (9U)

#define	GTZC_CFGR1_DMAMUX_Msk (0x01UL << GTZC_CFGR1_DMAMUX_Pos)

#define	GTZC_CFGR1_FLASH_Pos (10U)

#define	GTZC_CFGR1_FLASH_Msk (0x01UL << GTZC_CFGR1_FLASH_Pos)

#define	GTZC_CFGR1_SRAM1_Pos (11U)

#define	GTZC_CFGR1_SRAM1_Msk (0x01UL << GTZC_CFGR1_SRAM1_Pos)

#define	GTZC_CFGR1_SRAM2_Pos (12U)

#define	GTZC_CFGR1_SRAM2_Msk (0x01UL << GTZC_CFGR1_SRAM2_Pos)

#define	GTZC_CFGR1_PKA_Pos (13U)

#define	GTZC_CFGR1_PKA_Msk (0x01UL << GTZC_CFGR1_PKA_Pos)

#define	TZSC_CR_LCK_Pos (0U)

#define	TZSC_CR_LCK_Msk (0x01UL << TZSC_CR_LCK_Pos)

#define	TZSC_SECCFGR1_ALL_Pos (0U)

#define	TZSC_SECCFGR1_ALL_Msk (0x0000200CU)

#define	TZSC_SECCFGR1_AESSEC_Pos GTZC_CFGR1_AES_Pos

#define	TZSC_SECCFGR1_AESSEC_Msk GTZC_CFGR1_AES_Msk

#define	TZSC_SECCFGR1_RNGSEC_Pos GTZC_CFGR1_RNG_Pos

#define	TZSC_SECCFGR1_RNGSEC_Msk GTZC_CFGR1_RNG_Msk

#define	TZSC_SECCFGR1_PKASEC_Pos GTZC_CFGR1_PKA_Pos

#define	TZSC_SECCFGR1_PKASEC_Msk GTZC_CFGR1_PKA_Msk

#define	TZSC_PRIVCFGR1_ALL_Pos (0U)

#define	TZSC_PRIVCFGR1_ALL_Msk (0x0000201CU)

#define	TZSC_PRIVCFGR1_AESPRIV_Pos GTZC_CFGR1_AES_Pos

#define	TZSC_PRIVCFGR1_AESPRIV_Msk GTZC_CFGR1_AES_Msk

#define	TZSC_PRIVCFGR1_RNGPRIV_Pos GTZC_CFGR1_RNG_Pos

#define	TZSC_PRIVCFGR1_RNGPRIV_Msk GTZC_CFGR1_RNG_Msk

#define	TZSC_PRIVCFGR1_SUBGHZSPIPRIV_Pos GTZC_CFGR1_SUBGHZSPI_Pos

#define	TZSC_PRIVCFGR1_SUBGHZSPIPRIV_Msk GTZC_CFGR1_SUBGHZSPI_Msk

#define	TZSC_PRIVCFGR1_PKAPRIV_Pos GTZC_CFGR1_PKA_Pos

#define	TZSC_PRIVCFGR1_PKAPRIV_Msk GTZC_CFGR1_PKA_Msk

#define	TZSC_MPCWM1_UPWMR_LGTH_Pos (16U)

#define	TZSC_MPCWM1_UPWMR_LGTH_Msk (0x0FFFUL << TZSC_MPCWM1_UPWMR_LGTH_Pos)

#define	TZSC_MPCWM1_UPWWMR_LGTH_Pos (16U)

#define	TZSC_MPCWM1_UPWWMR_LGTH_Msk (0x0FFFUL << TZSC_MPCWM1_UPWWMR_LGTH_Pos)

#define	TZSC_MPCWM2_UPWMR_LGTH_Pos (16U)

#define	TZSC_MPCWM2_UPWMR_LGTH_Msk (0x0FFFUL << TZSC_MPCWM2_UPWMR_LGTH_Pos)

#define	TZSC_MPCWM3_UPWMR_LGTH_Pos (16U)

#define	TZSC_MPCWM3_UPWMR_LGTH_Msk (0x0FFFUL << TZSC_MPCWM3_UPWMR_LGTH_Pos)

#define	TZIC_IER1_ALL_Msk 0x00003FFFu

#define	TZIC_IER1_TZICIE_Pos GTZC_CFGR1_TZIC_Pos

#define	TZIC_IER1_TZICIE_Msk GTZC_CFGR1_TZIC_Msk

#define	TZIC_IER1_TZSCIE_Pos GTZC_CFGR1_TZSC_Pos

#define	TZIC_IER1_TZSCIE_Msk GTZC_CFGR1_TZSC_Msk

#define	TZIC_IER1_AESIE_Pos GTZC_CFGR1_AES_Pos

#define	TZIC_IER1_AESIE_Msk GTZC_CFGR1_AES_Msk

#define	TZIC_IER1_RNGIE_Pos GTZC_CFGR1_RNG_Pos

#define	TZIC_IER1_RNGIE_Msk GTZC_CFGR1_RNG_Msk

#define	TZIC_IER1_SUBGHZSPIIE_Pos GTZC_CFGR1_SUBGHZSPI_Pos

#define	TZIC_IER1_SUBGHZSPIIE_Msk GTZC_CFGR1_SUBGHZSPI_Msk

#define	TZIC_IER1_PWRIE_Pos GTZC_CFGR1_PWR_Pos

#define	TZIC_IER1_PWRIE_Msk GTZC_CFGR1_PWR_Msk

#define	TZIC_IER1_FLASHIFIE_Pos GTZC_CFGR1_FLASHIF_Pos

#define	TZIC_IER1_FLASHIFIE_Msk GTZC_CFGR1_FLASHIF_Msk

#define	TZIC_IER1_DMA1IE_Pos GTZC_CFGR1_DMA1_Pos

#define	TZIC_IER1_DMA1IE_Msk GTZC_CFGR1_DMA1_Msk

#define	TZIC_IER1_DMA2IE_Pos GTZC_CFGR1_DMA2_Pos

#define	TZIC_IER1_DMA2IE_Msk GTZC_CFGR1_DMA2_Msk

#define	TZIC_IER1_DMAMUXIE_Pos GTZC_CFGR1_DMAMUX_Pos

#define	TZIC_IER1_DMAMUXIE_Msk GTZC_CFGR1_DMAMUX_Msk

#define	TZIC_IER1_FLASHIE_Pos GTZC_CFGR1_FLASH_Pos

#define	TZIC_IER1_FLASHIE_Msk GTZC_CFGR1_FLASH_Msk

#define	TZIC_IER1_SRAM1IE_Pos GTZC_CFGR1_SRAM1_Pos

#define	TZIC_IER1_SRAM1IE_Msk GTZC_CFGR1_SRAM1_Msk

#define	TZIC_IER1_SRAM2IE_Pos GTZC_CFGR1_SRAM2_Pos

#define	TZIC_IER1_SRAM2IE_Msk GTZC_CFGR1_SRAM2_Msk

#define	TZIC_IER1_PKAIE_Pos GTZC_CFGR1_PKA_Pos

#define	TZIC_IER1_PKAIE_Msk GTZC_CFGR1_PKA_Msk

#define	TZIC_MISR1_TZICMF_Pos GTZC_CFGR1_TZIC_Pos

#define	TZIC_MISR1_TZICMF_Msk GTZC_CFGR1_TZIC_Msk

#define	TZIC_MISR1_TZSCMF_Pos GTZC_CFGR1_TZSC_Pos

#define	TZIC_MISR1_TZSCMF_Msk GTZC_CFGR1_TZSC_Msk

#define	TZIC_MISR1_AESMF_Pos GTZC_CFGR1_AES_Pos

#define	TZIC_MISR1_AESMF_Msk GTZC_CFGR1_AES_Msk

#define	TZIC_MISR1_RNGMF_Pos GTZC_CFGR1_RNG_Pos

#define	TZIC_MISR1_RNGMF_Msk GTZC_CFGR1_RNG_Msk

#define	TZIC_MISR1_SUBGHZSPIMF_Pos GTZC_CFGR1_SUBGHZSPI_Pos

#define	TZIC_MISR1_SUBGHZSPIMF_Msk GTZC_CFGR1_SUBGHZSPI_Msk

#define	TZIC_MISR1_PWRMF_Pos GTZC_CFGR1_PWR_Pos

#define	TZIC_MISR1_PWRMF_Msk GTZC_CFGR1_PWR_Msk

#define	TZIC_MISR1_FLASHIFMF_Pos GTZC_CFGR1_FLASHIF_Pos

#define	TZIC_MISR1_FLASHIFMF_Msk GTZC_CFGR1_FLASHIF_Msk

#define	TZIC_MISR1_DMA1MF_Pos GTZC_CFGR1_DMA1_Pos

#define	TZIC_MISR1_DMA1MF_Msk GTZC_CFGR1_DMA1_Msk

#define	TZIC_MISR1_DMA2MF_Pos GTZC_CFGR1_DMA2_Pos

#define	TZIC_MISR1_DMA2MF_Msk GTZC_CFGR1_DMA2_Msk

#define	TZIC_MISR1_DMAMUXMF_Pos GTZC_CFGR1_DMAMUX_Pos

#define	TZIC_MISR1_DMAMUXMF_Msk GTZC_CFGR1_DMAMUX_Msk

#define	TZIC_MISR1_FLASHMF_Pos GTZC_CFGR1_FLASH_Pos

#define	TZIC_MISR1_FLASHMF_Msk GTZC_CFGR1_FLASH_Msk

#define	TZIC_MISR1_SRAM1MF_Pos GTZC_CFGR1_SRAM1_Pos

#define	TZIC_MISR1_SRAM1MF_Msk GTZC_CFGR1_SRAM1_Msk

#define	TZIC_MISR1_SRAM2MF_Pos GTZC_CFGR1_SRAM2_Pos

#define	TZIC_MISR1_SRAM2MF_Msk GTZC_CFGR1_SRAM2_Msk

#define	TZIC_MISR1_PKAMF_Pos GTZC_CFGR1_PKA_Pos

#define	TZIC_MISR1_PKAMF_Msk GTZC_CFGR1_PKA_Msk

#define	TZIC_ICR1_TZICCF_Pos GTZC_CFGR1_TZIC_Pos

#define	TZIC_ICR1_TZICCF_Msk GTZC_CFGR1_TZIC_Msk

#define	TZIC_ICR1_TZSCCF_Pos GTZC_CFGR1_TZSC_Pos

#define	TZIC_ICR1_TZSCCF_Msk GTZC_CFGR1_TZSC_Msk

#define	TZIC_ICR1_AESCF_Pos GTZC_CFGR1_AES_Pos

#define	TZIC_ICR1_AESCF_Msk GTZC_CFGR1_AES_Msk

#define	TZIC_ICR1_RNGCF_Pos GTZC_CFGR1_RNG_Pos

#define	TZIC_ICR1_RNGCF_Msk GTZC_CFGR1_RNG_Msk

#define	TZIC_ICR1_SUBGHZSPICF_Pos GTZC_CFGR1_SUBGHZSPI_Pos

#define	TZIC_ICR1_SUBGHZSPICF_Msk GTZC_CFGR1_SUBGHZSPI_Msk

#define	TZIC_ICR1_PWRCF_Pos GTZC_CFGR1_PWR_Pos

#define	TZIC_ICR1_PWRCF_Msk GTZC_CFGR1_PWR_Msk

#define	TZIC_ICR1_FLASHIFCF_Pos GTZC_CFGR1_FLASHIF_Pos

#define	TZIC_ICR1_FLASHIFCF_Msk GTZC_CFGR1_FLASHIF_Msk

#define	TZIC_ICR1_DMA1CF_Pos GTZC_CFGR1_DMA1_Pos

#define	TZIC_ICR1_DMA1CF_Msk GTZC_CFGR1_DMA1_Msk

#define	TZIC_ICR1_DMA2CF_Pos GTZC_CFGR1_DMA2_Pos

#define	TZIC_ICR1_DMA2CF_Msk GTZC_CFGR1_DMA2_Msk

#define	TZIC_ICR1_DMAMUXCF_Pos GTZC_CFGR1_DMAMUX_Pos

#define	TZIC_ICR1_DMAMUXCF_Msk GTZC_CFGR1_DMAMUX_Msk

#define	TZIC_ICR1_FLASHCF_Pos GTZC_CFGR1_FLASH_Pos

#define	TZIC_ICR1_FLASHCF_Msk GTZC_CFGR1_FLASH_Msk

#define	TZIC_ICR1_SRAM1CF_Pos GTZC_CFGR1_SRAM1_Pos

#define	TZIC_ICR1_SRAM1CF_Msk GTZC_CFGR1_SRAM1_Msk

#define	TZIC_ICR1_SRAM2CF_Pos GTZC_CFGR1_SRAM2_Pos

#define	TZIC_ICR1_SRAM2CF_Msk GTZC_CFGR1_SRAM2_Msk

#define	TZIC_ICR1_PKACF_Pos GTZC_CFGR1_PKA_Pos

#define	TZIC_ICR1_PKACF_Msk GTZC_CFGR1_PKA_Msk

#define	FLASH_ACR_LATENCY_Pos (0U)

#define	FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos)

#define	FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk

#define	FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos)

#define	FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos)

#define	FLASH_ACR_PRFTEN_Pos (8U)

#define	FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos)

#define	FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk

#define	FLASH_ACR_ICEN_Pos (9U)

#define	FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos)

#define	FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk

#define	FLASH_ACR_DCEN_Pos (10U)

#define	FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos)

#define	FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk

#define	FLASH_ACR_ICRST_Pos (11U)

#define	FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos)

#define	FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk

#define	FLASH_ACR_DCRST_Pos (12U)

#define	FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos)

#define	FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk

#define	FLASH_ACR_PES_Pos (15U)

#define	FLASH_ACR_PES_Msk (0x1UL << FLASH_ACR_PES_Pos)

#define	FLASH_ACR_PES FLASH_ACR_PES_Msk

#define	FLASH_ACR_EMPTY_Pos (16U)

#define	FLASH_ACR_EMPTY_Msk (0x1UL << FLASH_ACR_EMPTY_Pos)

#define	FLASH_ACR_EMPTY FLASH_ACR_EMPTY_Msk

#define	FLASH_ACR2_PRIVMODE_Pos (0U)

#define	FLASH_ACR2_PRIVMODE_Msk (0x1UL << FLASH_ACR2_PRIVMODE_Pos)

#define	FLASH_ACR2_PRIVMODE FLASH_ACR2_PRIVMODE_Msk

#define	FLASH_ACR2_HDPADIS_Pos (1U)

#define	FLASH_ACR2_HDPADIS_Msk (0x1UL << FLASH_ACR2_HDPADIS_Pos)

#define	FLASH_ACR2_HDPADIS FLASH_ACR2_HDPADIS_Msk

#define	FLASH_ACR2_C2SWDBGEN_Pos (2U)

#define	FLASH_ACR2_C2SWDBGEN_Msk (0x1UL << FLASH_ACR2_C2SWDBGEN_Pos

#define	FLASH_ACR2_C2SWDBGEN FLASH_ACR2_C2SWDBGEN_Msk

#define	FLASH_SR_EOP_Pos (0U)

#define	FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)

#define	FLASH_SR_EOP FLASH_SR_EOP_Msk

#define	FLASH_SR_OPERR_Pos (1U)

#define	FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos)

#define	FLASH_SR_OPERR FLASH_SR_OPERR_Msk

#define	FLASH_SR_PROGERR_Pos (3U)

#define	FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos)

#define	FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk

#define	FLASH_SR_WRPERR_Pos (4U)

#define	FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos)

#define	FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk

#define	FLASH_SR_PGAERR_Pos (5U)

#define	FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos)

#define	FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk

#define	FLASH_SR_SIZERR_Pos (6U)

#define	FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos)

#define	FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk

#define	FLASH_SR_PGSERR_Pos (7U)

#define	FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos)

#define	FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk

#define	FLASH_SR_MISERR_Pos (8U)

#define	FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos)

#define	FLASH_SR_MISERR FLASH_SR_MISERR_Msk

#define	FLASH_SR_FASTERR_Pos (9U)

#define	FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos)

#define	FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk

#define	FLASH_SR_OPTNV_Pos (13U)

#define	FLASH_SR_OPTNV_Msk (0x1UL << FLASH_SR_OPTNV_Pos)

#define	FLASH_SR_OPTNV FLASH_SR_OPTNV_Msk

#define	FLASH_SR_RDERR_Pos (14U)

#define	FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos)

#define	FLASH_SR_RDERR FLASH_SR_RDERR_Msk

#define	FLASH_SR_OPTVERR_Pos (15U)

#define	FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos)

#define	FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk

#define	FLASH_SR_BSY_Pos (16U)

#define	FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)

#define	FLASH_SR_BSY FLASH_SR_BSY_Msk

#define	FLASH_SR_CFGBSY_Pos (18U)

#define	FLASH_SR_CFGBSY_Msk (0x1UL << FLASH_SR_CFGBSY_Pos)

#define	FLASH_SR_CFGBSY FLASH_SR_CFGBSY_Msk

#define	FLASH_SR_PESD_Pos (19U)

#define	FLASH_SR_PESD_Msk (0x1UL << FLASH_SR_PESD_Pos)

#define	FLASH_SR_PESD FLASH_SR_PESD_Msk

#define	FLASH_CR_PG_Pos (0U)

#define	FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)

#define	FLASH_CR_PG FLASH_CR_PG_Msk

#define	FLASH_CR_PER_Pos (1U)

#define	FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos)

#define	FLASH_CR_PER FLASH_CR_PER_Msk

#define	FLASH_CR_MER_Pos (2U)

#define	FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos)

#define	FLASH_CR_MER FLASH_CR_MER_Msk

#define	FLASH_CR_PNB_Pos (3U)

#define	FLASH_CR_PNB_Msk (0x7FUL << FLASH_CR_PNB_Pos)

#define	FLASH_CR_PNB FLASH_CR_PNB_Msk

#define	FLASH_CR_STRT_Pos (16U)

#define	FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos)

#define	FLASH_CR_STRT FLASH_CR_STRT_Msk

#define	FLASH_CR_OPTSTRT_Pos (17U)

#define	FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos)

#define	FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk

#define	FLASH_CR_FSTPG_Pos (18U)

#define	FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos)

#define	FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk

#define	FLASH_CR_EOPIE_Pos (24U)

#define	FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)

#define	FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk

#define	FLASH_CR_ERRIE_Pos (25U)

#define	FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos)

#define	FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk

#define	FLASH_CR_RDERRIE_Pos (26U)

#define	FLASH_CR_RDERRIE_Msk (0x1UL << FLASH_CR_RDERRIE_Pos)

#define	FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk

#define	FLASH_CR_OBL_LAUNCH_Pos (27U)

#define	FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos)

#define	FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk

#define	FLASH_CR_OPTLOCK_Pos (30U)

#define	FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos)

#define	FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk

#define	FLASH_CR_LOCK_Pos (31U)

#define	FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)

#define	FLASH_CR_LOCK FLASH_CR_LOCK_Msk

#define	FLASH_ECCR_ADDR_ECC_Pos (0U)

#define	FLASH_ECCR_ADDR_ECC_Msk (0x1FFFFUL << FLASH_ECCR_ADDR_ECC_Pos

#define	FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk

#define	FLASH_ECCR_SYSF_ECC_Pos (20U)

#define	FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos)

#define	FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk

#define	FLASH_ECCR_ECCCIE_Pos (24U)

#define	FLASH_ECCR_ECCCIE_Msk (0x1UL << FLASH_ECCR_ECCCIE_Pos)

#define	FLASH_ECCR_ECCCIE FLASH_ECCR_ECCCIE_Msk

#define	FLASH_ECCR_CPUID_Pos (26U)

#define	FLASH_ECCR_CPUID_Msk (0x7UL << FLASH_ECCR_CPUID_Pos)

#define	FLASH_ECCR_CPUID FLASH_ECCR_CPUID_Msk

#define	FLASH_ECCR_ECCC_Pos (30U)

#define	FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos)

#define	FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk

#define	FLASH_ECCR_ECCD_Pos (31U)

#define	FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos)

#define	FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk

#define	FLASH_OPTR_RDP_Pos (0U)

#define	FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos)

#define	FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk

#define	FLASH_OPTR_ESE_Pos (8U)

#define	FLASH_OPTR_ESE_Msk (0x1UL << FLASH_OPTR_ESE_Pos)

#define	FLASH_OPTR_ESE FLASH_OPTR_ESE_Msk

#define	FLASH_OPTR_BOR_LEV_Pos (9U)

#define	FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos)

#define	FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk

#define	FLASH_OPTR_BOR_LEV_0 (0x1UL << FLASH_OPTR_BOR_LEV_Pos)

#define	FLASH_OPTR_BOR_LEV_1 (0x2UL << FLASH_OPTR_BOR_LEV_Pos)

#define	FLASH_OPTR_BOR_LEV_2 (0x4UL << FLASH_OPTR_BOR_LEV_Pos)

#define	FLASH_OPTR_nRST_STOP_Pos (12U)

#define	FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos

#define	FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk

#define	FLASH_OPTR_nRST_STDBY_Pos (13U)

#define	FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos

#define	FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk

#define	FLASH_OPTR_nRST_SHDW_Pos (14U)

#define	FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos

#define	FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk

#define	FLASH_OPTR_IWDG_SW_Pos (16U)

#define	FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos)

#define	FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk

#define	FLASH_OPTR_IWDG_STOP_Pos (17U)

#define	FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos

#define	FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk

#define	FLASH_OPTR_IWDG_STDBY_Pos (18U)

#define	FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos

#define	FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk

#define	FLASH_OPTR_WWDG_SW_Pos (19U)

#define	FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos)

#define	FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk

#define	FLASH_OPTR_nBOOT1_Pos (23U)

#define	FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos)

#define	FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk

#define	FLASH_OPTR_SRAM2_PE_Pos (24U)

#define	FLASH_OPTR_SRAM2_PE_Msk (0x1UL << FLASH_OPTR_SRAM2_PE_Pos)

#define	FLASH_OPTR_SRAM2_PE FLASH_OPTR_SRAM2_PE_Msk

#define	FLASH_OPTR_SRAM_RST_Pos (25U)

#define	FLASH_OPTR_SRAM_RST_Msk (0x1UL << FLASH_OPTR_SRAM_RST_Pos)

#define	FLASH_OPTR_SRAM_RST FLASH_OPTR_SRAM_RST_Msk

#define	FLASH_OPTR_nSWBOOT0_Pos (26U)

#define	FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos)

#define	FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk

#define	FLASH_OPTR_nBOOT0_Pos (27U)

#define	FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos)

#define	FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk

#define	FLASH_OPTR_BOOT_LOCK_Pos (30U)

#define	FLASH_OPTR_BOOT_LOCK_Msk (0x1UL << FLASH_OPTR_BOOT_LOCK_Pos

#define	FLASH_OPTR_BOOT_LOCK FLASH_OPTR_BOOT_LOCK_Msk

#define	FLASH_OPTR_C2BOOT_LOCK_Pos (31U)

#define	FLASH_OPTR_C2BOOT_LOCK_Msk (0x1UL << FLASH_OPTR_C2BOOT_LOCK_Pos

#define	FLASH_OPTR_C2BOOT_LOCK FLASH_OPTR_C2BOOT_LOCK_Msk

#define	FLASH_PCROP1ASR_PCROP1A_STRT_Pos (0U)

#define	FLASH_PCROP1ASR_PCROP1A_STRT_Msk (0xFFUL << FLASH_PCROP1ASR_PCROP1A_STRT_Pos

#define	FLASH_PCROP1ASR_PCROP1A_STRT FLASH_PCROP1ASR_PCROP1A_STRT_Msk

#define	FLASH_PCROP1AER_PCROP1A_END_Pos (0U)

#define	FLASH_PCROP1AER_PCROP1A_END_Msk (0xFFUL << FLASH_PCROP1AER_PCROP1A_END_Pos

#define	FLASH_PCROP1AER_PCROP1A_END FLASH_PCROP1AER_PCROP1A_END_Msk

#define	FLASH_PCROP1AER_PCROP_RDP_Pos (31U)

#define	FLASH_PCROP1AER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1AER_PCROP_RDP_Pos

#define	FLASH_PCROP1AER_PCROP_RDP FLASH_PCROP1AER_PCROP_RDP_Msk

#define	FLASH_WRP1AR_WRP1A_STRT_Pos (0U)

#define	FLASH_WRP1AR_WRP1A_STRT_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_STRT_Pos

#define	FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk

#define	FLASH_WRP1AR_WRP1A_END_Pos (16U)

#define	FLASH_WRP1AR_WRP1A_END_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_END_Pos

#define	FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk

#define	FLASH_WRP1BR_WRP1B_STRT_Pos (0U)

#define	FLASH_WRP1BR_WRP1B_STRT_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_STRT_Pos

#define	FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk

#define	FLASH_WRP1BR_WRP1B_END_Pos (16U)

#define	FLASH_WRP1BR_WRP1B_END_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_END_Pos

#define	FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk

#define	FLASH_PCROP1BSR_PCROP1B_STRT_Pos (0U)

#define	FLASH_PCROP1BSR_PCROP1B_STRT_Msk (0xFFUL << FLASH_PCROP1BSR_PCROP1B_STRT_Pos

#define	FLASH_PCROP1BSR_PCROP1B_STRT FLASH_PCROP1BSR_PCROP1B_STRT_Msk

#define	FLASH_PCROP1BER_PCROP1B_END_Pos (0U)

#define	FLASH_PCROP1BER_PCROP1B_END_Msk (0xFFUL << FLASH_PCROP1BER_PCROP1B_END_Pos

#define	FLASH_PCROP1BER_PCROP1B_END FLASH_PCROP1BER_PCROP1B_END_Msk

#define	FLASH_IPCCBR_IPCCDBA_Pos (0U)

#define	FLASH_IPCCBR_IPCCDBA_Msk (0x3FFFUL << FLASH_IPCCBR_IPCCDBA_Pos

#define	FLASH_IPCCBR_IPCCDBA FLASH_IPCCBR_IPCCDBA_Msk

#define	FLASH_C2ACR_PRFTEN_Pos (8U)

#define	FLASH_C2ACR_PRFTEN_Msk (0x1UL << FLASH_C2ACR_PRFTEN_Pos)

#define	FLASH_C2ACR_PRFTEN FLASH_C2ACR_PRFTEN_Msk

#define	FLASH_C2ACR_ICEN_Pos (9U)

#define	FLASH_C2ACR_ICEN_Msk (0x1UL << FLASH_C2ACR_ICEN_Pos)

#define	FLASH_C2ACR_ICEN FLASH_C2ACR_ICEN_Msk

#define	FLASH_C2ACR_ICRST_Pos (11U)

#define	FLASH_C2ACR_ICRST_Msk (0x1UL << FLASH_C2ACR_ICRST_Pos)

#define	FLASH_C2ACR_ICRST FLASH_C2ACR_ICRST_Msk

#define	FLASH_C2ACR_PES_Pos (15U)

#define	FLASH_C2ACR_PES_Msk (0x1UL << FLASH_C2ACR_PES_Pos)

#define	FLASH_C2ACR_PES FLASH_C2ACR_PES_Msk

#define	FLASH_C2SR_EOP_Pos (0U)

#define	FLASH_C2SR_EOP_Msk (0x1UL << FLASH_C2SR_EOP_Pos)

#define	FLASH_C2SR_EOP FLASH_C2SR_EOP_Msk

#define	FLASH_C2SR_OPERR_Pos (1U)

#define	FLASH_C2SR_OPERR_Msk (0x1UL << FLASH_C2SR_OPERR_Pos)

#define	FLASH_C2SR_OPERR FLASH_C2SR_OPERR_Msk

#define	FLASH_C2SR_PROGERR_Pos (3U)

#define	FLASH_C2SR_PROGERR_Msk (0x1UL << FLASH_C2SR_PROGERR_Pos)

#define	FLASH_C2SR_PROGERR FLASH_C2SR_PROGERR_Msk

#define	FLASH_C2SR_WRPERR_Pos (4U)

#define	FLASH_C2SR_WRPERR_Msk (0x1UL << FLASH_C2SR_WRPERR_Pos)

#define	FLASH_C2SR_WRPERR FLASH_C2SR_WRPERR_Msk

#define	FLASH_C2SR_PGAERR_Pos (5U)

#define	FLASH_C2SR_PGAERR_Msk (0x1UL << FLASH_C2SR_PGAERR_Pos)

#define	FLASH_C2SR_PGAERR FLASH_C2SR_PGAERR_Msk

#define	FLASH_C2SR_SIZERR_Pos (6U)

#define	FLASH_C2SR_SIZERR_Msk (0x1UL << FLASH_C2SR_SIZERR_Pos)

#define	FLASH_C2SR_SIZERR FLASH_C2SR_SIZERR_Msk

#define	FLASH_C2SR_PGSERR_Pos (7U)

#define	FLASH_C2SR_PGSERR_Msk (0x1UL << FLASH_C2SR_PGSERR_Pos)

#define	FLASH_C2SR_PGSERR FLASH_C2SR_PGSERR_Msk

#define	FLASH_C2SR_MISERR_Pos (8U)

#define	FLASH_C2SR_MISERR_Msk (0x1UL << FLASH_C2SR_MISERR_Pos)

#define	FLASH_C2SR_MISERR FLASH_C2SR_MISERR_Msk

#define	FLASH_C2SR_FASTERR_Pos (9U)

#define	FLASH_C2SR_FASTERR_Msk (0x1UL << FLASH_C2SR_FASTERR_Pos)

#define	FLASH_C2SR_FASTERR FLASH_C2SR_FASTERR_Msk

#define	FLASH_C2SR_RDERR_Pos (14U)

#define	FLASH_C2SR_RDERR_Msk (0x1UL << FLASH_C2SR_RDERR_Pos)

#define	FLASH_C2SR_RDERR FLASH_C2SR_RDERR_Msk

#define	FLASH_C2SR_BSY_Pos (16U)

#define	FLASH_C2SR_BSY_Msk (0x1UL << FLASH_C2SR_BSY_Pos)

#define	FLASH_C2SR_BSY FLASH_C2SR_BSY_Msk

#define	FLASH_C2SR_CFGBSY_Pos (18U)

#define	FLASH_C2SR_CFGBSY_Msk (0x1UL << FLASH_C2SR_CFGBSY_Pos)

#define	FLASH_C2SR_CFGBSY FLASH_C2SR_CFGBSY_Msk

#define	FLASH_C2SR_PESD_Pos (19U)

#define	FLASH_C2SR_PESD_Msk (0x1UL << FLASH_C2SR_PESD_Pos)

#define	FLASH_C2SR_PESD FLASH_C2SR_PESD_Msk

#define	FLASH_C2CR_PG_Pos (0U)

#define	FLASH_C2CR_PG_Msk (0x1UL << FLASH_C2CR_PG_Pos)

#define	FLASH_C2CR_PG FLASH_C2CR_PG_Msk

#define	FLASH_C2CR_PER_Pos (1U)

#define	FLASH_C2CR_PER_Msk (0x1UL << FLASH_C2CR_PER_Pos)

#define	FLASH_C2CR_PER FLASH_C2CR_PER_Msk

#define	FLASH_C2CR_MER_Pos (2U)

#define	FLASH_C2CR_MER_Msk (0x1UL << FLASH_C2CR_MER_Pos)

#define	FLASH_C2CR_MER FLASH_C2CR_MER_Msk

#define	FLASH_C2CR_PNB_Pos (3U)

#define	FLASH_C2CR_PNB_Msk (0xFFUL << FLASH_C2CR_PNB_Pos)

#define	FLASH_C2CR_PNB FLASH_C2CR_PNB_Msk

#define	FLASH_C2CR_STRT_Pos (16U)

#define	FLASH_C2CR_STRT_Msk (0x1UL << FLASH_C2CR_STRT_Pos)

#define	FLASH_C2CR_STRT FLASH_C2CR_STRT_Msk

#define	FLASH_C2CR_FSTPG_Pos (18U)

#define	FLASH_C2CR_FSTPG_Msk (0x1UL << FLASH_C2CR_FSTPG_Pos)

#define	FLASH_C2CR_FSTPG FLASH_C2CR_FSTPG_Msk

#define	FLASH_C2CR_EOPIE_Pos (24U)

#define	FLASH_C2CR_EOPIE_Msk (0x1UL << FLASH_C2CR_EOPIE_Pos)

#define	FLASH_C2CR_EOPIE FLASH_C2CR_EOPIE_Msk

#define	FLASH_C2CR_ERRIE_Pos (25U)

#define	FLASH_C2CR_ERRIE_Msk (0x1UL << FLASH_C2CR_ERRIE_Pos)

#define	FLASH_C2CR_ERRIE FLASH_C2CR_ERRIE_Msk

#define	FLASH_C2CR_RDERRIE_Pos (26U)

#define	FLASH_C2CR_RDERRIE_Msk (0x1UL << FLASH_C2CR_RDERRIE_Pos)

#define	FLASH_C2CR_RDERRIE FLASH_C2CR_RDERRIE_Msk

#define	FLASH_SFR_SFSA_Pos (0U)

#define	FLASH_SFR_SFSA_Msk (0x7FUL << FLASH_SFR_SFSA_Pos)

#define	FLASH_SFR_SFSA FLASH_SFR_SFSA_Msk /* Secure flash start address */

#define	FLASH_SFR_FSD_Pos (7U)

#define	FLASH_SFR_FSD_Msk (0x1UL << FLASH_SFR_FSD_Pos)

#define	FLASH_SFR_FSD FLASH_SFR_FSD_Msk /* Flash mode secure */

#define	FLASH_SFR_DDS_Pos (12U)

#define	FLASH_SFR_DDS_Msk (0x1UL << FLASH_SFR_DDS_Pos)

#define	FLASH_SFR_DDS FLASH_SFR_DDS_Msk /* Enabling and disabling CPU2 Debug access */

#define	FLASH_SFR_HDPSA_Pos (16U)

#define	FLASH_SFR_HDPSA_Msk (0x7FUL << FLASH_SFR_HDPSA_Pos)

#define	FLASH_SFR_HDPSA FLASH_SFR_HDPSA_Msk

#define	FLASH_SFR_HDPAD_Pos (23U)

#define	FLASH_SFR_HDPAD_Msk (0x1UL << FLASH_SFR_HDPAD_Pos)

#define	FLASH_SFR_HDPAD FLASH_SFR_HDPAD_Msk /* User Flash Hide Protection Area disabled */

#define	FLASH_SFR_SUBGHZSPISD_Pos (31U)

#define	FLASH_SFR_SUBGHZSPISD_Msk (0x1UL << FLASH_SFR_SUBGHZSPISD_Pos)

#define	FLASH_SFR_SUBGHZSPISD FLASH_SFR_SUBGHZSPISD_Msk /* Sub-GHz radio SPI security disable */

#define	FLASH_SRRVR_SBRV_Pos (0U)

#define	FLASH_SRRVR_SBRV_Msk (0xFFFFUL << FLASH_SRRVR_SBRV_Pos)

#define	FLASH_SRRVR_SBRV FLASH_SRRVR_SBRV_Msk /* SCPU2 boot reset vector memory offset */

#define	FLASH_SRRVR_SBRSA_Pos (18U)

#define	FLASH_SRRVR_SBRSA_Msk (0x1FUL << FLASH_SRRVR_SBRSA_Pos)

#define	FLASH_SRRVR_SBRSA FLASH_SRRVR_SBRSA_Msk /* Secure backup SRAM2 start address */

#define	FLASH_SRRVR_BRSD_Pos (23U)

#define	FLASH_SRRVR_BRSD_Msk (0x1UL << FLASH_SRRVR_BRSD_Pos)

#define	FLASH_SRRVR_BRSD FLASH_SRRVR_BRSD_Msk /* Backup SRAM2 secure mode */

#define	FLASH_SRRVR_SNBRSA_Pos (25U)

#define	FLASH_SRRVR_SNBRSA_Msk (0x1FUL << FLASH_SRRVR_SNBRSA_Pos)

#define	FLASH_SRRVR_SNBRSA FLASH_SRRVR_SNBRSA_Msk /* Secure non-backup SRAM1 start address */

#define	FLASH_SRRVR_NBRSD_Pos (30U)

#define	FLASH_SRRVR_NBRSD_Msk (0x1UL << FLASH_SRRVR_NBRSD_Pos)

#define	FLASH_SRRVR_NBRSD FLASH_SRRVR_NBRSD_Msk /* Non-backup SRAM1 secure mode */

#define	FLASH_SRRVR_C2OPT_Pos (31U)

#define	FLASH_SRRVR_C2OPT_Msk (0x1UL << FLASH_SRRVR_C2OPT_Pos)

#define	FLASH_SRRVR_C2OPT FLASH_SRRVR_C2OPT_Msk /* SCPU2 boot reset vector memory selection */

#define	GPIO_MODER_MODE0_Pos (0U)

#define	GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos)

#define	GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk

#define	GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos)

#define	GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos)

#define	GPIO_MODER_MODE1_Pos (2U)

#define	GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos)

#define	GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk

#define	GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos)

#define	GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos)

#define	GPIO_MODER_MODE2_Pos (4U)

#define	GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos)

#define	GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk

#define	GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos)

#define	GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos)

#define	GPIO_MODER_MODE3_Pos (6U)

#define	GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos)

#define	GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk

#define	GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos)

#define	GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos)

#define	GPIO_MODER_MODE4_Pos (8U)

#define	GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos)

#define	GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk

#define	GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos)

#define	GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos)

#define	GPIO_MODER_MODE5_Pos (10U)

#define	GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos)

#define	GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk

#define	GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos)

#define	GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos)

#define	GPIO_MODER_MODE6_Pos (12U)

#define	GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos)

#define	GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk

#define	GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos)

#define	GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos)

#define	GPIO_MODER_MODE7_Pos (14U)

#define	GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos)

#define	GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk

#define	GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos)

#define	GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos)

#define	GPIO_MODER_MODE8_Pos (16U)

#define	GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos)

#define	GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk

#define	GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos)

#define	GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos)

#define	GPIO_MODER_MODE9_Pos (18U)

#define	GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos)

#define	GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk

#define	GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos)

#define	GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos)

#define	GPIO_MODER_MODE10_Pos (20U)

#define	GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos)

#define	GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk

#define	GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos)

#define	GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos)

#define	GPIO_MODER_MODE11_Pos (22U)

#define	GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos)

#define	GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk

#define	GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos)

#define	GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos)

#define	GPIO_MODER_MODE12_Pos (24U)

#define	GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos)

#define	GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk

#define	GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos)

#define	GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos)

#define	GPIO_MODER_MODE13_Pos (26U)

#define	GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos)

#define	GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk

#define	GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos)

#define	GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos)

#define	GPIO_MODER_MODE14_Pos (28U)

#define	GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos)

#define	GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk

#define	GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos)

#define	GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos)

#define	GPIO_MODER_MODE15_Pos (30U)

#define	GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos)

#define	GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk

#define	GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos)

#define	GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos)

#define	GPIO_OTYPER_OT0_Pos (0U)

#define	GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos)

#define	GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk

#define	GPIO_OTYPER_OT1_Pos (1U)

#define	GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos)

#define	GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk

#define	GPIO_OTYPER_OT2_Pos (2U)

#define	GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos)

#define	GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk

#define	GPIO_OTYPER_OT3_Pos (3U)

#define	GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos)

#define	GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk

#define	GPIO_OTYPER_OT4_Pos (4U)

#define	GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos)

#define	GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk

#define	GPIO_OTYPER_OT5_Pos (5U)

#define	GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos)

#define	GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk

#define	GPIO_OTYPER_OT6_Pos (6U)

#define	GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos)

#define	GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk

#define	GPIO_OTYPER_OT7_Pos (7U)

#define	GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos)

#define	GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk

#define	GPIO_OTYPER_OT8_Pos (8U)

#define	GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos)

#define	GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk

#define	GPIO_OTYPER_OT9_Pos (9U)

#define	GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos)

#define	GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk

#define	GPIO_OTYPER_OT10_Pos (10U)

#define	GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos)

#define	GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk

#define	GPIO_OTYPER_OT11_Pos (11U)

#define	GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos)

#define	GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk

#define	GPIO_OTYPER_OT12_Pos (12U)

#define	GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos)

#define	GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk

#define	GPIO_OTYPER_OT13_Pos (13U)

#define	GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos)

#define	GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk

#define	GPIO_OTYPER_OT14_Pos (14U)

#define	GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos)

#define	GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk

#define	GPIO_OTYPER_OT15_Pos (15U)

#define	GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos)

#define	GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk

#define	GPIO_OSPEEDR_OSPEED0_Pos (0U)

#define	GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)

#define	GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk

#define	GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)

#define	GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)

#define	GPIO_OSPEEDR_OSPEED1_Pos (2U)

#define	GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)

#define	GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk

#define	GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)

#define	GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)

#define	GPIO_OSPEEDR_OSPEED2_Pos (4U)

#define	GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)

#define	GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk

#define	GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)

#define	GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)

#define	GPIO_OSPEEDR_OSPEED3_Pos (6U)

#define	GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)

#define	GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk

#define	GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)

#define	GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)

#define	GPIO_OSPEEDR_OSPEED4_Pos (8U)

#define	GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)

#define	GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk

#define	GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)

#define	GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)

#define	GPIO_OSPEEDR_OSPEED5_Pos (10U)

#define	GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)

#define	GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk

#define	GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)

#define	GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)

#define	GPIO_OSPEEDR_OSPEED6_Pos (12U)

#define	GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)

#define	GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk

#define	GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)

#define	GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)

#define	GPIO_OSPEEDR_OSPEED7_Pos (14U)

#define	GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)

#define	GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk

#define	GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)

#define	GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)

#define	GPIO_OSPEEDR_OSPEED8_Pos (16U)

#define	GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)

#define	GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk

#define	GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)

#define	GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)

#define	GPIO_OSPEEDR_OSPEED9_Pos (18U)

#define	GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)

#define	GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk

#define	GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)

#define	GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)

#define	GPIO_OSPEEDR_OSPEED10_Pos (20U)

#define	GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)

#define	GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk

#define	GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)

#define	GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)

#define	GPIO_OSPEEDR_OSPEED11_Pos (22U)

#define	GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)

#define	GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk

#define	GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)

#define	GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)

#define	GPIO_OSPEEDR_OSPEED12_Pos (24U)

#define	GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)

#define	GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk

#define	GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)

#define	GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)

#define	GPIO_OSPEEDR_OSPEED13_Pos (26U)

#define	GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)

#define	GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk

#define	GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)

#define	GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)

#define	GPIO_OSPEEDR_OSPEED14_Pos (28U)

#define	GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)

#define	GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk

#define	GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)

#define	GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)

#define	GPIO_OSPEEDR_OSPEED15_Pos (30U)

#define	GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)

#define	GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk

#define	GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)

#define	GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)

#define	GPIO_PUPDR_PUPD0_Pos (0U)

#define	GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos)

#define	GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk

#define	GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos)

#define	GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos)

#define	GPIO_PUPDR_PUPD1_Pos (2U)

#define	GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos)

#define	GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk

#define	GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos)

#define	GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos)

#define	GPIO_PUPDR_PUPD2_Pos (4U)

#define	GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos)

#define	GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk

#define	GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos)

#define	GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos)

#define	GPIO_PUPDR_PUPD3_Pos (6U)

#define	GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos)

#define	GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk

#define	GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos)

#define	GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos)

#define	GPIO_PUPDR_PUPD4_Pos (8U)

#define	GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos)

#define	GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk

#define	GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos)

#define	GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos)

#define	GPIO_PUPDR_PUPD5_Pos (10U)

#define	GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos)

#define	GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk

#define	GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos)

#define	GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos)

#define	GPIO_PUPDR_PUPD6_Pos (12U)

#define	GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos)

#define	GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk

#define	GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos)

#define	GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos)

#define	GPIO_PUPDR_PUPD7_Pos (14U)

#define	GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos)

#define	GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk

#define	GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos)

#define	GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos)

#define	GPIO_PUPDR_PUPD8_Pos (16U)

#define	GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos)

#define	GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk

#define	GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos)

#define	GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos)

#define	GPIO_PUPDR_PUPD9_Pos (18U)

#define	GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos)

#define	GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk

#define	GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos)

#define	GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos)

#define	GPIO_PUPDR_PUPD10_Pos (20U)

#define	GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos)

#define	GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk

#define	GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos)

#define	GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos)

#define	GPIO_PUPDR_PUPD11_Pos (22U)

#define	GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos)

#define	GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk

#define	GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos)

#define	GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos)

#define	GPIO_PUPDR_PUPD12_Pos (24U)

#define	GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos)

#define	GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk

#define	GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos)

#define	GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos)

#define	GPIO_PUPDR_PUPD13_Pos (26U)

#define	GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos)

#define	GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk

#define	GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos)

#define	GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos)

#define	GPIO_PUPDR_PUPD14_Pos (28U)

#define	GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos)

#define	GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk

#define	GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos)

#define	GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos)

#define	GPIO_PUPDR_PUPD15_Pos (30U)

#define	GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos)

#define	GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk

#define	GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos)

#define	GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos)

#define	GPIO_IDR_ID0_Pos (0U)

#define	GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos)

#define	GPIO_IDR_ID0 GPIO_IDR_ID0_Msk

#define	GPIO_IDR_ID1_Pos (1U)

#define	GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos)

#define	GPIO_IDR_ID1 GPIO_IDR_ID1_Msk

#define	GPIO_IDR_ID2_Pos (2U)

#define	GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos)

#define	GPIO_IDR_ID2 GPIO_IDR_ID2_Msk

#define	GPIO_IDR_ID3_Pos (3U)

#define	GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos)

#define	GPIO_IDR_ID3 GPIO_IDR_ID3_Msk

#define	GPIO_IDR_ID4_Pos (4U)

#define	GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos)

#define	GPIO_IDR_ID4 GPIO_IDR_ID4_Msk

#define	GPIO_IDR_ID5_Pos (5U)

#define	GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos)

#define	GPIO_IDR_ID5 GPIO_IDR_ID5_Msk

#define	GPIO_IDR_ID6_Pos (6U)

#define	GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos)

#define	GPIO_IDR_ID6 GPIO_IDR_ID6_Msk

#define	GPIO_IDR_ID7_Pos (7U)

#define	GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos)

#define	GPIO_IDR_ID7 GPIO_IDR_ID7_Msk

#define	GPIO_IDR_ID8_Pos (8U)

#define	GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos)

#define	GPIO_IDR_ID8 GPIO_IDR_ID8_Msk

#define	GPIO_IDR_ID9_Pos (9U)

#define	GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos)

#define	GPIO_IDR_ID9 GPIO_IDR_ID9_Msk

#define	GPIO_IDR_ID10_Pos (10U)

#define	GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos)

#define	GPIO_IDR_ID10 GPIO_IDR_ID10_Msk

#define	GPIO_IDR_ID11_Pos (11U)

#define	GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos)

#define	GPIO_IDR_ID11 GPIO_IDR_ID11_Msk

#define	GPIO_IDR_ID12_Pos (12U)

#define	GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos)

#define	GPIO_IDR_ID12 GPIO_IDR_ID12_Msk

#define	GPIO_IDR_ID13_Pos (13U)

#define	GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos)

#define	GPIO_IDR_ID13 GPIO_IDR_ID13_Msk

#define	GPIO_IDR_ID14_Pos (14U)

#define	GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos)

#define	GPIO_IDR_ID14 GPIO_IDR_ID14_Msk

#define	GPIO_IDR_ID15_Pos (15U)

#define	GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos)

#define	GPIO_IDR_ID15 GPIO_IDR_ID15_Msk

#define	GPIO_ODR_OD0_Pos (0U)

#define	GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos)

#define	GPIO_ODR_OD0 GPIO_ODR_OD0_Msk

#define	GPIO_ODR_OD1_Pos (1U)

#define	GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos)

#define	GPIO_ODR_OD1 GPIO_ODR_OD1_Msk

#define	GPIO_ODR_OD2_Pos (2U)

#define	GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos)

#define	GPIO_ODR_OD2 GPIO_ODR_OD2_Msk

#define	GPIO_ODR_OD3_Pos (3U)

#define	GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos)

#define	GPIO_ODR_OD3 GPIO_ODR_OD3_Msk

#define	GPIO_ODR_OD4_Pos (4U)

#define	GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos)

#define	GPIO_ODR_OD4 GPIO_ODR_OD4_Msk

#define	GPIO_ODR_OD5_Pos (5U)

#define	GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos)

#define	GPIO_ODR_OD5 GPIO_ODR_OD5_Msk

#define	GPIO_ODR_OD6_Pos (6U)

#define	GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos)

#define	GPIO_ODR_OD6 GPIO_ODR_OD6_Msk

#define	GPIO_ODR_OD7_Pos (7U)

#define	GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos)

#define	GPIO_ODR_OD7 GPIO_ODR_OD7_Msk

#define	GPIO_ODR_OD8_Pos (8U)

#define	GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos)

#define	GPIO_ODR_OD8 GPIO_ODR_OD8_Msk

#define	GPIO_ODR_OD9_Pos (9U)

#define	GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos)

#define	GPIO_ODR_OD9 GPIO_ODR_OD9_Msk

#define	GPIO_ODR_OD10_Pos (10U)

#define	GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos)

#define	GPIO_ODR_OD10 GPIO_ODR_OD10_Msk

#define	GPIO_ODR_OD11_Pos (11U)

#define	GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos)

#define	GPIO_ODR_OD11 GPIO_ODR_OD11_Msk

#define	GPIO_ODR_OD12_Pos (12U)

#define	GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos)

#define	GPIO_ODR_OD12 GPIO_ODR_OD12_Msk

#define	GPIO_ODR_OD13_Pos (13U)

#define	GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos)

#define	GPIO_ODR_OD13 GPIO_ODR_OD13_Msk

#define	GPIO_ODR_OD14_Pos (14U)

#define	GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos)

#define	GPIO_ODR_OD14 GPIO_ODR_OD14_Msk

#define	GPIO_ODR_OD15_Pos (15U)

#define	GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos)

#define	GPIO_ODR_OD15 GPIO_ODR_OD15_Msk

#define	GPIO_BSRR_BS0_Pos (0U)

#define	GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos)

#define	GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk

#define	GPIO_BSRR_BS1_Pos (1U)

#define	GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos)

#define	GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk

#define	GPIO_BSRR_BS2_Pos (2U)

#define	GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos)

#define	GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk

#define	GPIO_BSRR_BS3_Pos (3U)

#define	GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos)

#define	GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk

#define	GPIO_BSRR_BS4_Pos (4U)

#define	GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos)

#define	GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk

#define	GPIO_BSRR_BS5_Pos (5U)

#define	GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos)

#define	GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk

#define	GPIO_BSRR_BS6_Pos (6U)

#define	GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos)

#define	GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk

#define	GPIO_BSRR_BS7_Pos (7U)

#define	GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos)

#define	GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk

#define	GPIO_BSRR_BS8_Pos (8U)

#define	GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos)

#define	GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk

#define	GPIO_BSRR_BS9_Pos (9U)

#define	GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos)

#define	GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk

#define	GPIO_BSRR_BS10_Pos (10U)

#define	GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos)

#define	GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk

#define	GPIO_BSRR_BS11_Pos (11U)

#define	GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos)

#define	GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk

#define	GPIO_BSRR_BS12_Pos (12U)

#define	GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos)

#define	GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk

#define	GPIO_BSRR_BS13_Pos (13U)

#define	GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos)

#define	GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk

#define	GPIO_BSRR_BS14_Pos (14U)

#define	GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos)

#define	GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk

#define	GPIO_BSRR_BS15_Pos (15U)

#define	GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos)

#define	GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk

#define	GPIO_BSRR_BR0_Pos (16U)

#define	GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos)

#define	GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk

#define	GPIO_BSRR_BR1_Pos (17U)

#define	GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos)

#define	GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk

#define	GPIO_BSRR_BR2_Pos (18U)

#define	GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos)

#define	GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk

#define	GPIO_BSRR_BR3_Pos (19U)

#define	GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos)

#define	GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk

#define	GPIO_BSRR_BR4_Pos (20U)

#define	GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos)

#define	GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk

#define	GPIO_BSRR_BR5_Pos (21U)

#define	GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos)

#define	GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk

#define	GPIO_BSRR_BR6_Pos (22U)

#define	GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos)

#define	GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk

#define	GPIO_BSRR_BR7_Pos (23U)

#define	GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos)

#define	GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk

#define	GPIO_BSRR_BR8_Pos (24U)

#define	GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos)

#define	GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk

#define	GPIO_BSRR_BR9_Pos (25U)

#define	GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos)

#define	GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk

#define	GPIO_BSRR_BR10_Pos (26U)

#define	GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos)

#define	GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk

#define	GPIO_BSRR_BR11_Pos (27U)

#define	GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos)

#define	GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk

#define	GPIO_BSRR_BR12_Pos (28U)

#define	GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos)

#define	GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk

#define	GPIO_BSRR_BR13_Pos (29U)

#define	GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos)

#define	GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk

#define	GPIO_BSRR_BR14_Pos (30U)

#define	GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos)

#define	GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk

#define	GPIO_BSRR_BR15_Pos (31U)

#define	GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos)

#define	GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk

#define	GPIO_LCKR_LCK0_Pos (0U)

#define	GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)

#define	GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk

#define	GPIO_LCKR_LCK1_Pos (1U)

#define	GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)

#define	GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk

#define	GPIO_LCKR_LCK2_Pos (2U)

#define	GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)

#define	GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk

#define	GPIO_LCKR_LCK3_Pos (3U)

#define	GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)

#define	GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk

#define	GPIO_LCKR_LCK4_Pos (4U)

#define	GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)

#define	GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk

#define	GPIO_LCKR_LCK5_Pos (5U)

#define	GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)

#define	GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk

#define	GPIO_LCKR_LCK6_Pos (6U)

#define	GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)

#define	GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk

#define	GPIO_LCKR_LCK7_Pos (7U)

#define	GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)

#define	GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk

#define	GPIO_LCKR_LCK8_Pos (8U)

#define	GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)

#define	GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk

#define	GPIO_LCKR_LCK9_Pos (9U)

#define	GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)

#define	GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk

#define	GPIO_LCKR_LCK10_Pos (10U)

#define	GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)

#define	GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk

#define	GPIO_LCKR_LCK11_Pos (11U)

#define	GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)

#define	GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk

#define	GPIO_LCKR_LCK12_Pos (12U)

#define	GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)

#define	GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk

#define	GPIO_LCKR_LCK13_Pos (13U)

#define	GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)

#define	GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk

#define	GPIO_LCKR_LCK14_Pos (14U)

#define	GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)

#define	GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk

#define	GPIO_LCKR_LCK15_Pos (15U)

#define	GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)

#define	GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk

#define	GPIO_LCKR_LCKK_Pos (16U)

#define	GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)

#define	GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk

#define	GPIO_AFRL_AFSEL0_Pos (0U)

#define	GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos)

#define	GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk

#define	GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos)

#define	GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos)

#define	GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos)

#define	GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos)

#define	GPIO_AFRL_AFSEL1_Pos (4U)

#define	GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos)

#define	GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk

#define	GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos)

#define	GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos)

#define	GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos)

#define	GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos)

#define	GPIO_AFRL_AFSEL2_Pos (8U)

#define	GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos)

#define	GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk

#define	GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos)

#define	GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos)

#define	GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos)

#define	GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos)

#define	GPIO_AFRL_AFSEL3_Pos (12U)

#define	GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos)

#define	GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk

#define	GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos)

#define	GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos)

#define	GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos)

#define	GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos)

#define	GPIO_AFRL_AFSEL4_Pos (16U)

#define	GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos)

#define	GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk

#define	GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos)

#define	GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos)

#define	GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos)

#define	GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos)

#define	GPIO_AFRL_AFSEL5_Pos (20U)

#define	GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos)

#define	GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk

#define	GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos)

#define	GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos)

#define	GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos)

#define	GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos)

#define	GPIO_AFRL_AFSEL6_Pos (24U)

#define	GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos)

#define	GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk

#define	GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos)

#define	GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos)

#define	GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos)

#define	GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos)

#define	GPIO_AFRL_AFSEL7_Pos (28U)

#define	GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos)

#define	GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk

#define	GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos)

#define	GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos)

#define	GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos)

#define	GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos)

#define	GPIO_AFRH_AFSEL8_Pos (0U)

#define	GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos)

#define	GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk

#define	GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos)

#define	GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos)

#define	GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos)

#define	GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos)

#define	GPIO_AFRH_AFSEL9_Pos (4U)

#define	GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos)

#define	GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk

#define	GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos)

#define	GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos)

#define	GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos)

#define	GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos)

#define	GPIO_AFRH_AFSEL10_Pos (8U)

#define	GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos)

#define	GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk

#define	GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos)

#define	GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos)

#define	GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos)

#define	GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos)

#define	GPIO_AFRH_AFSEL11_Pos (12U)

#define	GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos)

#define	GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk

#define	GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos)

#define	GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos)

#define	GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos)

#define	GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos)

#define	GPIO_AFRH_AFSEL12_Pos (16U)

#define	GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos)

#define	GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk

#define	GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos)

#define	GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos)

#define	GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos)

#define	GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos)

#define	GPIO_AFRH_AFSEL13_Pos (20U)

#define	GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos)

#define	GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk

#define	GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos)

#define	GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos)

#define	GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos)

#define	GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos)

#define	GPIO_AFRH_AFSEL14_Pos (24U)

#define	GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos)

#define	GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk

#define	GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos)

#define	GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos)

#define	GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos)

#define	GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos)

#define	GPIO_AFRH_AFSEL15_Pos (28U)

#define	GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos)

#define	GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk

#define	GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos)

#define	GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos)

#define	GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos)

#define	GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos)

#define	GPIO_BRR_BR0_Pos (0U)

#define	GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos)

#define	GPIO_BRR_BR0 GPIO_BRR_BR0_Msk

#define	GPIO_BRR_BR1_Pos (1U)

#define	GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos)

#define	GPIO_BRR_BR1 GPIO_BRR_BR1_Msk

#define	GPIO_BRR_BR2_Pos (2U)

#define	GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos)

#define	GPIO_BRR_BR2 GPIO_BRR_BR2_Msk

#define	GPIO_BRR_BR3_Pos (3U)

#define	GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos)

#define	GPIO_BRR_BR3 GPIO_BRR_BR3_Msk

#define	GPIO_BRR_BR4_Pos (4U)

#define	GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos)

#define	GPIO_BRR_BR4 GPIO_BRR_BR4_Msk

#define	GPIO_BRR_BR5_Pos (5U)

#define	GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos)

#define	GPIO_BRR_BR5 GPIO_BRR_BR5_Msk

#define	GPIO_BRR_BR6_Pos (6U)

#define	GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos)

#define	GPIO_BRR_BR6 GPIO_BRR_BR6_Msk

#define	GPIO_BRR_BR7_Pos (7U)

#define	GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos)

#define	GPIO_BRR_BR7 GPIO_BRR_BR7_Msk

#define	GPIO_BRR_BR8_Pos (8U)

#define	GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos)

#define	GPIO_BRR_BR8 GPIO_BRR_BR8_Msk

#define	GPIO_BRR_BR9_Pos (9U)

#define	GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos)

#define	GPIO_BRR_BR9 GPIO_BRR_BR9_Msk

#define	GPIO_BRR_BR10_Pos (10U)

#define	GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos)

#define	GPIO_BRR_BR10 GPIO_BRR_BR10_Msk

#define	GPIO_BRR_BR11_Pos (11U)

#define	GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos)

#define	GPIO_BRR_BR11 GPIO_BRR_BR11_Msk

#define	GPIO_BRR_BR12_Pos (12U)

#define	GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos)

#define	GPIO_BRR_BR12 GPIO_BRR_BR12_Msk

#define	GPIO_BRR_BR13_Pos (13U)

#define	GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos)

#define	GPIO_BRR_BR13 GPIO_BRR_BR13_Msk

#define	GPIO_BRR_BR14_Pos (14U)

#define	GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos)

#define	GPIO_BRR_BR14 GPIO_BRR_BR14_Msk

#define	GPIO_BRR_BR15_Pos (15U)

#define	GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos)

#define	GPIO_BRR_BR15 GPIO_BRR_BR15_Msk

#define	HSEM_R_PROCID_Pos (0U)

#define	HSEM_R_PROCID_Msk (0xFFUL << HSEM_R_PROCID_Pos)

#define	HSEM_R_PROCID HSEM_R_PROCID_Msk

#define	HSEM_R_COREID_Pos (8U)

#define	HSEM_R_COREID_Msk (0xFUL << HSEM_R_COREID_Pos)

#define	HSEM_R_COREID HSEM_R_COREID_Msk

#define	HSEM_R_LOCK_Pos (31U)

#define	HSEM_R_LOCK_Msk (0x1UL << HSEM_R_LOCK_Pos)

#define	HSEM_R_LOCK HSEM_R_LOCK_Msk

#define	HSEM_RLR_PROCID_Pos (0U)

#define	HSEM_RLR_PROCID_Msk (0xFFUL << HSEM_RLR_PROCID_Pos)

#define	HSEM_RLR_PROCID HSEM_RLR_PROCID_Msk

#define	HSEM_RLR_COREID_Pos (8U)

#define	HSEM_RLR_COREID_Msk (0xFUL << HSEM_RLR_COREID_Pos)

#define	HSEM_RLR_COREID HSEM_RLR_COREID_Msk

#define	HSEM_RLR_LOCK_Pos (31U)

#define	HSEM_RLR_LOCK_Msk (0x1UL << HSEM_RLR_LOCK_Pos)

#define	HSEM_RLR_LOCK HSEM_RLR_LOCK_Msk

#define	HSEM_C1IER_ISE0_Pos (0U)

#define	HSEM_C1IER_ISE0_Msk (0x1UL << HSEM_C1IER_ISE0_Pos)

#define	HSEM_C1IER_ISE0 HSEM_C1IER_ISE0_Msk

#define	HSEM_C1IER_ISE1_Pos (1U)

#define	HSEM_C1IER_ISE1_Msk (0x1UL << HSEM_C1IER_ISE1_Pos)

#define	HSEM_C1IER_ISE1 HSEM_C1IER_ISE1_Msk

#define	HSEM_C1IER_ISE2_Pos (2U)

#define	HSEM_C1IER_ISE2_Msk (0x1UL << HSEM_C1IER_ISE2_Pos)

#define	HSEM_C1IER_ISE2 HSEM_C1IER_ISE2_Msk

#define	HSEM_C1IER_ISE3_Pos (3U)

#define	HSEM_C1IER_ISE3_Msk (0x1UL << HSEM_C1IER_ISE3_Pos)

#define	HSEM_C1IER_ISE3 HSEM_C1IER_ISE3_Msk

#define	HSEM_C1IER_ISE4_Pos (4U)

#define	HSEM_C1IER_ISE4_Msk (0x1UL << HSEM_C1IER_ISE4_Pos)

#define	HSEM_C1IER_ISE4 HSEM_C1IER_ISE4_Msk

#define	HSEM_C1IER_ISE5_Pos (5U)

#define	HSEM_C1IER_ISE5_Msk (0x1UL << HSEM_C1IER_ISE5_Pos)

#define	HSEM_C1IER_ISE5 HSEM_C1IER_ISE5_Msk

#define	HSEM_C1IER_ISE6_Pos (6U)

#define	HSEM_C1IER_ISE6_Msk (0x1UL << HSEM_C1IER_ISE6_Pos)

#define	HSEM_C1IER_ISE6 HSEM_C1IER_ISE6_Msk

#define	HSEM_C1IER_ISE7_Pos (7U)

#define	HSEM_C1IER_ISE7_Msk (0x1UL << HSEM_C1IER_ISE7_Pos)

#define	HSEM_C1IER_ISE7 HSEM_C1IER_ISE7_Msk

#define	HSEM_C1IER_ISE8_Pos (8U)

#define	HSEM_C1IER_ISE8_Msk (0x1UL << HSEM_C1IER_ISE8_Pos)

#define	HSEM_C1IER_ISE8 HSEM_C1IER_ISE8_Msk

#define	HSEM_C1IER_ISE9_Pos (9U)

#define	HSEM_C1IER_ISE9_Msk (0x1UL << HSEM_C1IER_ISE9_Pos)

#define	HSEM_C1IER_ISE9 HSEM_C1IER_ISE9_Msk

#define	HSEM_C1IER_ISE10_Pos (10U)

#define	HSEM_C1IER_ISE10_Msk (0x1UL << HSEM_C1IER_ISE10_Pos)

#define	HSEM_C1IER_ISE10 HSEM_C1IER_ISE10_Msk

#define	HSEM_C1IER_ISE11_Pos (11U)

#define	HSEM_C1IER_ISE11_Msk (0x1UL << HSEM_C1IER_ISE11_Pos)

#define	HSEM_C1IER_ISE11 HSEM_C1IER_ISE11_Msk

#define	HSEM_C1IER_ISE12_Pos (12U)

#define	HSEM_C1IER_ISE12_Msk (0x1UL << HSEM_C1IER_ISE12_Pos)

#define	HSEM_C1IER_ISE12 HSEM_C1IER_ISE12_Msk

#define	HSEM_C1IER_ISE13_Pos (13U)

#define	HSEM_C1IER_ISE13_Msk (0x1UL << HSEM_C1IER_ISE13_Pos)

#define	HSEM_C1IER_ISE13 HSEM_C1IER_ISE13_Msk

#define	HSEM_C1IER_ISE14_Pos (14U)

#define	HSEM_C1IER_ISE14_Msk (0x1UL << HSEM_C1IER_ISE14_Pos)

#define	HSEM_C1IER_ISE14 HSEM_C1IER_ISE14_Msk

#define	HSEM_C1IER_ISE15_Pos (15U)

#define	HSEM_C1IER_ISE15_Msk (0x1UL << HSEM_C1IER_ISE15_Pos)

#define	HSEM_C1IER_ISE15 HSEM_C1IER_ISE15_Msk

#define	HSEM_C1ICR_ISC0_Pos (0U)

#define	HSEM_C1ICR_ISC0_Msk (0x1UL << HSEM_C1ICR_ISC0_Pos)

#define	HSEM_C1ICR_ISC0 HSEM_C1ICR_ISC0_Msk

#define	HSEM_C1ICR_ISC1_Pos (1U)

#define	HSEM_C1ICR_ISC1_Msk (0x1UL << HSEM_C1ICR_ISC1_Pos)

#define	HSEM_C1ICR_ISC1 HSEM_C1ICR_ISC1_Msk

#define	HSEM_C1ICR_ISC2_Pos (2U)

#define	HSEM_C1ICR_ISC2_Msk (0x1UL << HSEM_C1ICR_ISC2_Pos)

#define	HSEM_C1ICR_ISC2 HSEM_C1ICR_ISC2_Msk

#define	HSEM_C1ICR_ISC3_Pos (3U)

#define	HSEM_C1ICR_ISC3_Msk (0x1UL << HSEM_C1ICR_ISC3_Pos)

#define	HSEM_C1ICR_ISC3 HSEM_C1ICR_ISC3_Msk

#define	HSEM_C1ICR_ISC4_Pos (4U)

#define	HSEM_C1ICR_ISC4_Msk (0x1UL << HSEM_C1ICR_ISC4_Pos)

#define	HSEM_C1ICR_ISC4 HSEM_C1ICR_ISC4_Msk

#define	HSEM_C1ICR_ISC5_Pos (5U)

#define	HSEM_C1ICR_ISC5_Msk (0x1UL << HSEM_C1ICR_ISC5_Pos)

#define	HSEM_C1ICR_ISC5 HSEM_C1ICR_ISC5_Msk

#define	HSEM_C1ICR_ISC6_Pos (6U)

#define	HSEM_C1ICR_ISC6_Msk (0x1UL << HSEM_C1ICR_ISC6_Pos)

#define	HSEM_C1ICR_ISC6 HSEM_C1ICR_ISC6_Msk

#define	HSEM_C1ICR_ISC7_Pos (7U)

#define	HSEM_C1ICR_ISC7_Msk (0x1UL << HSEM_C1ICR_ISC7_Pos)

#define	HSEM_C1ICR_ISC7 HSEM_C1ICR_ISC7_Msk

#define	HSEM_C1ICR_ISC8_Pos (8U)

#define	HSEM_C1ICR_ISC8_Msk (0x1UL << HSEM_C1ICR_ISC8_Pos)

#define	HSEM_C1ICR_ISC8 HSEM_C1ICR_ISC8_Msk

#define	HSEM_C1ICR_ISC9_Pos (9U)

#define	HSEM_C1ICR_ISC9_Msk (0x1UL << HSEM_C1ICR_ISC9_Pos)

#define	HSEM_C1ICR_ISC9 HSEM_C1ICR_ISC9_Msk

#define	HSEM_C1ICR_ISC10_Pos (10U)

#define	HSEM_C1ICR_ISC10_Msk (0x1UL << HSEM_C1ICR_ISC10_Pos)

#define	HSEM_C1ICR_ISC10 HSEM_C1ICR_ISC10_Msk

#define	HSEM_C1ICR_ISC11_Pos (11U)

#define	HSEM_C1ICR_ISC11_Msk (0x1UL << HSEM_C1ICR_ISC11_Pos)

#define	HSEM_C1ICR_ISC11 HSEM_C1ICR_ISC11_Msk

#define	HSEM_C1ICR_ISC12_Pos (12U)

#define	HSEM_C1ICR_ISC12_Msk (0x1UL << HSEM_C1ICR_ISC12_Pos)

#define	HSEM_C1ICR_ISC12 HSEM_C1ICR_ISC12_Msk

#define	HSEM_C1ICR_ISC13_Pos (13U)

#define	HSEM_C1ICR_ISC13_Msk (0x1UL << HSEM_C1ICR_ISC13_Pos)

#define	HSEM_C1ICR_ISC13 HSEM_C1ICR_ISC13_Msk

#define	HSEM_C1ICR_ISC14_Pos (14U)

#define	HSEM_C1ICR_ISC14_Msk (0x1UL << HSEM_C1ICR_ISC14_Pos)

#define	HSEM_C1ICR_ISC14 HSEM_C1ICR_ISC14_Msk

#define	HSEM_C1ICR_ISC15_Pos (15U)

#define	HSEM_C1ICR_ISC15_Msk (0x1UL << HSEM_C1ICR_ISC15_Pos)

#define	HSEM_C1ICR_ISC15 HSEM_C1ICR_ISC15_Msk

#define	HSEM_C1ISR_ISF0_Pos (0U)

#define	HSEM_C1ISR_ISF0_Msk (0x1UL << HSEM_C1ISR_ISF0_Pos)

#define	HSEM_C1ISR_ISF0 HSEM_C1ISR_ISF0_Msk

#define	HSEM_C1ISR_ISF1_Pos (1U)

#define	HSEM_C1ISR_ISF1_Msk (0x1UL << HSEM_C1ISR_ISF1_Pos)

#define	HSEM_C1ISR_ISF1 HSEM_C1ISR_ISF1_Msk

#define	HSEM_C1ISR_ISF2_Pos (2U)

#define	HSEM_C1ISR_ISF2_Msk (0x1UL << HSEM_C1ISR_ISF2_Pos)

#define	HSEM_C1ISR_ISF2 HSEM_C1ISR_ISF2_Msk

#define	HSEM_C1ISR_ISF3_Pos (3U)

#define	HSEM_C1ISR_ISF3_Msk (0x1UL << HSEM_C1ISR_ISF3_Pos)

#define	HSEM_C1ISR_ISF3 HSEM_C1ISR_ISF3_Msk

#define	HSEM_C1ISR_ISF4_Pos (4U)

#define	HSEM_C1ISR_ISF4_Msk (0x1UL << HSEM_C1ISR_ISF4_Pos)

#define	HSEM_C1ISR_ISF4 HSEM_C1ISR_ISF4_Msk

#define	HSEM_C1ISR_ISF5_Pos (5U)

#define	HSEM_C1ISR_ISF5_Msk (0x1UL << HSEM_C1ISR_ISF5_Pos)

#define	HSEM_C1ISR_ISF5 HSEM_C1ISR_ISF5_Msk

#define	HSEM_C1ISR_ISF6_Pos (6U)

#define	HSEM_C1ISR_ISF6_Msk (0x1UL << HSEM_C1ISR_ISF6_Pos)

#define	HSEM_C1ISR_ISF6 HSEM_C1ISR_ISF6_Msk

#define	HSEM_C1ISR_ISF7_Pos (7U)

#define	HSEM_C1ISR_ISF7_Msk (0x1UL << HSEM_C1ISR_ISF7_Pos)

#define	HSEM_C1ISR_ISF7 HSEM_C1ISR_ISF7_Msk

#define	HSEM_C1ISR_ISF8_Pos (8U)

#define	HSEM_C1ISR_ISF8_Msk (0x1UL << HSEM_C1ISR_ISF8_Pos)

#define	HSEM_C1ISR_ISF8 HSEM_C1ISR_ISF8_Msk

#define	HSEM_C1ISR_ISF9_Pos (9U)

#define	HSEM_C1ISR_ISF9_Msk (0x1UL << HSEM_C1ISR_ISF9_Pos)

#define	HSEM_C1ISR_ISF9 HSEM_C1ISR_ISF9_Msk

#define	HSEM_C1ISR_ISF10_Pos (10U)

#define	HSEM_C1ISR_ISF10_Msk (0x1UL << HSEM_C1ISR_ISF10_Pos)

#define	HSEM_C1ISR_ISF10 HSEM_C1ISR_ISF10_Msk

#define	HSEM_C1ISR_ISF11_Pos (11U)

#define	HSEM_C1ISR_ISF11_Msk (0x1UL << HSEM_C1ISR_ISF11_Pos)

#define	HSEM_C1ISR_ISF11 HSEM_C1ISR_ISF11_Msk

#define	HSEM_C1ISR_ISF12_Pos (12U)

#define	HSEM_C1ISR_ISF12_Msk (0x1UL << HSEM_C1ISR_ISF12_Pos)

#define	HSEM_C1ISR_ISF12 HSEM_C1ISR_ISF12_Msk

#define	HSEM_C1ISR_ISF13_Pos (13U)

#define	HSEM_C1ISR_ISF13_Msk (0x1UL << HSEM_C1ISR_ISF13_Pos)

#define	HSEM_C1ISR_ISF13 HSEM_C1ISR_ISF13_Msk

#define	HSEM_C1ISR_ISF14_Pos (14U)

#define	HSEM_C1ISR_ISF14_Msk (0x1UL << HSEM_C1ISR_ISF14_Pos)

#define	HSEM_C1ISR_ISF14 HSEM_C1ISR_ISF14_Msk

#define	HSEM_C1ISR_ISF15_Pos (15U)

#define	HSEM_C1ISR_ISF15_Msk (0x1UL << HSEM_C1ISR_ISF15_Pos)

#define	HSEM_C1ISR_ISF15 HSEM_C1ISR_ISF15_Msk

#define	HSEM_C1MISR_MISF0_Pos (0U)

#define	HSEM_C1MISR_MISF0_Msk (0x1UL << HSEM_C1MISR_MISF0_Pos)

#define	HSEM_C1MISR_MISF0 HSEM_C1MISR_MISF0_Msk

#define	HSEM_C1MISR_MISF1_Pos (1U)

#define	HSEM_C1MISR_MISF1_Msk (0x1UL << HSEM_C1MISR_MISF1_Pos)

#define	HSEM_C1MISR_MISF1 HSEM_C1MISR_MISF1_Msk

#define	HSEM_C1MISR_MISF2_Pos (2U)

#define	HSEM_C1MISR_MISF2_Msk (0x1UL << HSEM_C1MISR_MISF2_Pos)

#define	HSEM_C1MISR_MISF2 HSEM_C1MISR_MISF2_Msk

#define	HSEM_C1MISR_MISF3_Pos (3U)

#define	HSEM_C1MISR_MISF3_Msk (0x1UL << HSEM_C1MISR_MISF3_Pos)

#define	HSEM_C1MISR_MISF3 HSEM_C1MISR_MISF3_Msk

#define	HSEM_C1MISR_MISF4_Pos (4U)

#define	HSEM_C1MISR_MISF4_Msk (0x1UL << HSEM_C1MISR_MISF4_Pos)

#define	HSEM_C1MISR_MISF4 HSEM_C1MISR_MISF4_Msk

#define	HSEM_C1MISR_MISF5_Pos (5U)

#define	HSEM_C1MISR_MISF5_Msk (0x1UL << HSEM_C1MISR_MISF5_Pos)

#define	HSEM_C1MISR_MISF5 HSEM_C1MISR_MISF5_Msk

#define	HSEM_C1MISR_MISF6_Pos (6U)

#define	HSEM_C1MISR_MISF6_Msk (0x1UL << HSEM_C1MISR_MISF6_Pos)

#define	HSEM_C1MISR_MISF6 HSEM_C1MISR_MISF6_Msk

#define	HSEM_C1MISR_MISF7_Pos (7U)

#define	HSEM_C1MISR_MISF7_Msk (0x1UL << HSEM_C1MISR_MISF7_Pos)

#define	HSEM_C1MISR_MISF7 HSEM_C1MISR_MISF7_Msk

#define	HSEM_C1MISR_MISF8_Pos (8U)

#define	HSEM_C1MISR_MISF8_Msk (0x1UL << HSEM_C1MISR_MISF8_Pos)

#define	HSEM_C1MISR_MISF8 HSEM_C1MISR_MISF8_Msk

#define	HSEM_C1MISR_MISF9_Pos (9U)

#define	HSEM_C1MISR_MISF9_Msk (0x1UL << HSEM_C1MISR_MISF9_Pos)

#define	HSEM_C1MISR_MISF9 HSEM_C1MISR_MISF9_Msk

#define	HSEM_C1MISR_MISF10_Pos (10U)

#define	HSEM_C1MISR_MISF10_Msk (0x1UL << HSEM_C1MISR_MISF10_Pos)

#define	HSEM_C1MISR_MISF10 HSEM_C1MISR_MISF10_Msk

#define	HSEM_C1MISR_MISF11_Pos (11U)

#define	HSEM_C1MISR_MISF11_Msk (0x1UL << HSEM_C1MISR_MISF11_Pos)

#define	HSEM_C1MISR_MISF11 HSEM_C1MISR_MISF11_Msk

#define	HSEM_C1MISR_MISF12_Pos (12U)

#define	HSEM_C1MISR_MISF12_Msk (0x1UL << HSEM_C1MISR_MISF12_Pos)

#define	HSEM_C1MISR_MISF12 HSEM_C1MISR_MISF12_Msk

#define	HSEM_C1MISR_MISF13_Pos (13U)

#define	HSEM_C1MISR_MISF13_Msk (0x1UL << HSEM_C1MISR_MISF13_Pos)

#define	HSEM_C1MISR_MISF13 HSEM_C1MISR_MISF13_Msk

#define	HSEM_C1MISR_MISF14_Pos (14U)

#define	HSEM_C1MISR_MISF14_Msk (0x1UL << HSEM_C1MISR_MISF14_Pos)

#define	HSEM_C1MISR_MISF14 HSEM_C1MISR_MISF14_Msk

#define	HSEM_C1MISR_MISF15_Pos (15U)

#define	HSEM_C1MISR_MISF15_Msk (0x1UL << HSEM_C1MISR_MISF15_Pos)

#define	HSEM_C1MISR_MISF15 HSEM_C1MISR_MISF15_Msk

#define	HSEM_C2IER_ISE0_Pos (0U)

#define	HSEM_C2IER_ISE0_Msk (0x1UL << HSEM_C2IER_ISE0_Pos)

#define	HSEM_C2IER_ISE0 HSEM_C2IER_ISE0_Msk

#define	HSEM_C2IER_ISE1_Pos (1U)

#define	HSEM_C2IER_ISE1_Msk (0x1UL << HSEM_C2IER_ISE1_Pos)

#define	HSEM_C2IER_ISE1 HSEM_C2IER_ISE1_Msk

#define	HSEM_C2IER_ISE2_Pos (2U)

#define	HSEM_C2IER_ISE2_Msk (0x1UL << HSEM_C2IER_ISE2_Pos)

#define	HSEM_C2IER_ISE2 HSEM_C2IER_ISE2_Msk

#define	HSEM_C2IER_ISE3_Pos (3U)

#define	HSEM_C2IER_ISE3_Msk (0x1UL << HSEM_C2IER_ISE3_Pos)

#define	HSEM_C2IER_ISE3 HSEM_C2IER_ISE3_Msk

#define	HSEM_C2IER_ISE4_Pos (4U)

#define	HSEM_C2IER_ISE4_Msk (0x1UL << HSEM_C2IER_ISE4_Pos)

#define	HSEM_C2IER_ISE4 HSEM_C2IER_ISE4_Msk

#define	HSEM_C2IER_ISE5_Pos (5U)

#define	HSEM_C2IER_ISE5_Msk (0x1UL << HSEM_C2IER_ISE5_Pos)

#define	HSEM_C2IER_ISE5 HSEM_C2IER_ISE5_Msk

#define	HSEM_C2IER_ISE6_Pos (6U)

#define	HSEM_C2IER_ISE6_Msk (0x1UL << HSEM_C2IER_ISE6_Pos)

#define	HSEM_C2IER_ISE6 HSEM_C2IER_ISE6_Msk

#define	HSEM_C2IER_ISE7_Pos (7U)

#define	HSEM_C2IER_ISE7_Msk (0x1UL << HSEM_C2IER_ISE7_Pos)

#define	HSEM_C2IER_ISE7 HSEM_C2IER_ISE7_Msk

#define	HSEM_C2IER_ISE8_Pos (8U)

#define	HSEM_C2IER_ISE8_Msk (0x1UL << HSEM_C2IER_ISE8_Pos)

#define	HSEM_C2IER_ISE8 HSEM_C2IER_ISE8_Msk

#define	HSEM_C2IER_ISE9_Pos (9U)

#define	HSEM_C2IER_ISE9_Msk (0x1UL << HSEM_C2IER_ISE9_Pos)

#define	HSEM_C2IER_ISE9 HSEM_C2IER_ISE9_Msk

#define	HSEM_C2IER_ISE10_Pos (10U)

#define	HSEM_C2IER_ISE10_Msk (0x1UL << HSEM_C2IER_ISE10_Pos)

#define	HSEM_C2IER_ISE10 HSEM_C2IER_ISE10_Msk

#define	HSEM_C2IER_ISE11_Pos (11U)

#define	HSEM_C2IER_ISE11_Msk (0x1UL << HSEM_C2IER_ISE11_Pos)

#define	HSEM_C2IER_ISE11 HSEM_C2IER_ISE11_Msk

#define	HSEM_C2IER_ISE12_Pos (12U)

#define	HSEM_C2IER_ISE12_Msk (0x1UL << HSEM_C2IER_ISE12_Pos)

#define	HSEM_C2IER_ISE12 HSEM_C2IER_ISE12_Msk

#define	HSEM_C2IER_ISE13_Pos (13U)

#define	HSEM_C2IER_ISE13_Msk (0x1UL << HSEM_C2IER_ISE13_Pos)

#define	HSEM_C2IER_ISE13 HSEM_C2IER_ISE13_Msk

#define	HSEM_C2IER_ISE14_Pos (14U)

#define	HSEM_C2IER_ISE14_Msk (0x1UL << HSEM_C2IER_ISE14_Pos)

#define	HSEM_C2IER_ISE14 HSEM_C2IER_ISE14_Msk

#define	HSEM_C2IER_ISE15_Pos (15U)

#define	HSEM_C2IER_ISE15_Msk (0x1UL << HSEM_C2IER_ISE15_Pos)

#define	HSEM_C2IER_ISE15 HSEM_C2IER_ISE15_Msk

#define	HSEM_C2ICR_ISC0_Pos (0U)

#define	HSEM_C2ICR_ISC0_Msk (0x1UL << HSEM_C2ICR_ISC0_Pos)

#define	HSEM_C2ICR_ISC0 HSEM_C2ICR_ISC0_Msk

#define	HSEM_C2ICR_ISC1_Pos (1U)

#define	HSEM_C2ICR_ISC1_Msk (0x1UL << HSEM_C2ICR_ISC1_Pos)

#define	HSEM_C2ICR_ISC1 HSEM_C2ICR_ISC1_Msk

#define	HSEM_C2ICR_ISC2_Pos (2U)

#define	HSEM_C2ICR_ISC2_Msk (0x1UL << HSEM_C2ICR_ISC2_Pos)

#define	HSEM_C2ICR_ISC2 HSEM_C2ICR_ISC2_Msk

#define	HSEM_C2ICR_ISC3_Pos (3U)

#define	HSEM_C2ICR_ISC3_Msk (0x1UL << HSEM_C2ICR_ISC3_Pos)

#define	HSEM_C2ICR_ISC3 HSEM_C2ICR_ISC3_Msk

#define	HSEM_C2ICR_ISC4_Pos (4U)

#define	HSEM_C2ICR_ISC4_Msk (0x1UL << HSEM_C2ICR_ISC4_Pos)

#define	HSEM_C2ICR_ISC4 HSEM_C2ICR_ISC4_Msk

#define	HSEM_C2ICR_ISC5_Pos (5U)

#define	HSEM_C2ICR_ISC5_Msk (0x1UL << HSEM_C2ICR_ISC5_Pos)

#define	HSEM_C2ICR_ISC5 HSEM_C2ICR_ISC5_Msk

#define	HSEM_C2ICR_ISC6_Pos (6U)

#define	HSEM_C2ICR_ISC6_Msk (0x1UL << HSEM_C2ICR_ISC6_Pos)

#define	HSEM_C2ICR_ISC6 HSEM_C2ICR_ISC6_Msk

#define	HSEM_C2ICR_ISC7_Pos (7U)

#define	HSEM_C2ICR_ISC7_Msk (0x1UL << HSEM_C2ICR_ISC7_Pos)

#define	HSEM_C2ICR_ISC7 HSEM_C2ICR_ISC7_Msk

#define	HSEM_C2ICR_ISC8_Pos (8U)

#define	HSEM_C2ICR_ISC8_Msk (0x1UL << HSEM_C2ICR_ISC8_Pos)

#define	HSEM_C2ICR_ISC8 HSEM_C2ICR_ISC8_Msk

#define	HSEM_C2ICR_ISC9_Pos (9U)

#define	HSEM_C2ICR_ISC9_Msk (0x1UL << HSEM_C2ICR_ISC9_Pos)

#define	HSEM_C2ICR_ISC9 HSEM_C2ICR_ISC9_Msk

#define	HSEM_C2ICR_ISC10_Pos (10U)

#define	HSEM_C2ICR_ISC10_Msk (0x1UL << HSEM_C2ICR_ISC10_Pos)

#define	HSEM_C2ICR_ISC10 HSEM_C2ICR_ISC10_Msk

#define	HSEM_C2ICR_ISC11_Pos (11U)

#define	HSEM_C2ICR_ISC11_Msk (0x1UL << HSEM_C2ICR_ISC11_Pos)

#define	HSEM_C2ICR_ISC11 HSEM_C2ICR_ISC11_Msk

#define	HSEM_C2ICR_ISC12_Pos (12U)

#define	HSEM_C2ICR_ISC12_Msk (0x1UL << HSEM_C2ICR_ISC12_Pos)

#define	HSEM_C2ICR_ISC12 HSEM_C2ICR_ISC12_Msk

#define	HSEM_C2ICR_ISC13_Pos (13U)

#define	HSEM_C2ICR_ISC13_Msk (0x1UL << HSEM_C2ICR_ISC13_Pos)

#define	HSEM_C2ICR_ISC13 HSEM_C2ICR_ISC13_Msk

#define	HSEM_C2ICR_ISC14_Pos (14U)

#define	HSEM_C2ICR_ISC14_Msk (0x1UL << HSEM_C2ICR_ISC14_Pos)

#define	HSEM_C2ICR_ISC14 HSEM_C2ICR_ISC14_Msk

#define	HSEM_C2ICR_ISC15_Pos (15U)

#define	HSEM_C2ICR_ISC15_Msk (0x1UL << HSEM_C2ICR_ISC15_Pos)

#define	HSEM_C2ICR_ISC15 HSEM_C2ICR_ISC15_Msk

#define	HSEM_C2ISR_ISF0_Pos (0U)

#define	HSEM_C2ISR_ISF0_Msk (0x1UL << HSEM_C2ISR_ISF0_Pos)

#define	HSEM_C2ISR_ISF0 HSEM_C2ISR_ISF0_Msk

#define	HSEM_C2ISR_ISF1_Pos (1U)

#define	HSEM_C2ISR_ISF1_Msk (0x1UL << HSEM_C2ISR_ISF1_Pos)

#define	HSEM_C2ISR_ISF1 HSEM_C2ISR_ISF1_Msk

#define	HSEM_C2ISR_ISF2_Pos (2U)

#define	HSEM_C2ISR_ISF2_Msk (0x1UL << HSEM_C2ISR_ISF2_Pos)

#define	HSEM_C2ISR_ISF2 HSEM_C2ISR_ISF2_Msk

#define	HSEM_C2ISR_ISF3_Pos (3U)

#define	HSEM_C2ISR_ISF3_Msk (0x1UL << HSEM_C2ISR_ISF3_Pos)

#define	HSEM_C2ISR_ISF3 HSEM_C2ISR_ISF3_Msk

#define	HSEM_C2ISR_ISF4_Pos (4U)

#define	HSEM_C2ISR_ISF4_Msk (0x1UL << HSEM_C2ISR_ISF4_Pos)

#define	HSEM_C2ISR_ISF4 HSEM_C2ISR_ISF4_Msk

#define	HSEM_C2ISR_ISF5_Pos (5U)

#define	HSEM_C2ISR_ISF5_Msk (0x1UL << HSEM_C2ISR_ISF5_Pos)

#define	HSEM_C2ISR_ISF5 HSEM_C2ISR_ISF5_Msk

#define	HSEM_C2ISR_ISF6_Pos (6U)

#define	HSEM_C2ISR_ISF6_Msk (0x1UL << HSEM_C2ISR_ISF6_Pos)

#define	HSEM_C2ISR_ISF6 HSEM_C2ISR_ISF6_Msk

#define	HSEM_C2ISR_ISF7_Pos (7U)

#define	HSEM_C2ISR_ISF7_Msk (0x1UL << HSEM_C2ISR_ISF7_Pos)

#define	HSEM_C2ISR_ISF7 HSEM_C2ISR_ISF7_Msk

#define	HSEM_C2ISR_ISF8_Pos (8U)

#define	HSEM_C2ISR_ISF8_Msk (0x1UL << HSEM_C2ISR_ISF8_Pos)

#define	HSEM_C2ISR_ISF8 HSEM_C2ISR_ISF8_Msk

#define	HSEM_C2ISR_ISF9_Pos (9U)

#define	HSEM_C2ISR_ISF9_Msk (0x1UL << HSEM_C2ISR_ISF9_Pos)

#define	HSEM_C2ISR_ISF9 HSEM_C2ISR_ISF9_Msk

#define	HSEM_C2ISR_ISF10_Pos (10U)

#define	HSEM_C2ISR_ISF10_Msk (0x1UL << HSEM_C2ISR_ISF10_Pos)

#define	HSEM_C2ISR_ISF10 HSEM_C2ISR_ISF10_Msk

#define	HSEM_C2ISR_ISF11_Pos (11U)

#define	HSEM_C2ISR_ISF11_Msk (0x1UL << HSEM_C2ISR_ISF11_Pos)

#define	HSEM_C2ISR_ISF11 HSEM_C2ISR_ISF11_Msk

#define	HSEM_C2ISR_ISF12_Pos (12U)

#define	HSEM_C2ISR_ISF12_Msk (0x1UL << HSEM_C2ISR_ISF12_Pos)

#define	HSEM_C2ISR_ISF12 HSEM_C2ISR_ISF12_Msk

#define	HSEM_C2ISR_ISF13_Pos (13U)

#define	HSEM_C2ISR_ISF13_Msk (0x1UL << HSEM_C2ISR_ISF13_Pos)

#define	HSEM_C2ISR_ISF13 HSEM_C2ISR_ISF13_Msk

#define	HSEM_C2ISR_ISF14_Pos (14U)

#define	HSEM_C2ISR_ISF14_Msk (0x1UL << HSEM_C2ISR_ISF14_Pos)

#define	HSEM_C2ISR_ISF14 HSEM_C2ISR_ISF14_Msk

#define	HSEM_C2ISR_ISF15_Pos (15U)

#define	HSEM_C2ISR_ISF15_Msk (0x1UL << HSEM_C2ISR_ISF15_Pos)

#define	HSEM_C2ISR_ISF15 HSEM_C2ISR_ISF15_Msk

#define	HSEM_C2MISR_MISF0_Pos (0U)

#define	HSEM_C2MISR_MISF0_Msk (0x1UL << HSEM_C2MISR_MISF0_Pos)

#define	HSEM_C2MISR_MISF0 HSEM_C2MISR_MISF0_Msk

#define	HSEM_C2MISR_MISF1_Pos (1U)

#define	HSEM_C2MISR_MISF1_Msk (0x1UL << HSEM_C2MISR_MISF1_Pos)

#define	HSEM_C2MISR_MISF1 HSEM_C2MISR_MISF1_Msk

#define	HSEM_C2MISR_MISF2_Pos (2U)

#define	HSEM_C2MISR_MISF2_Msk (0x1UL << HSEM_C2MISR_MISF2_Pos)

#define	HSEM_C2MISR_MISF2 HSEM_C2MISR_MISF2_Msk

#define	HSEM_C2MISR_MISF3_Pos (3U)

#define	HSEM_C2MISR_MISF3_Msk (0x1UL << HSEM_C2MISR_MISF3_Pos)

#define	HSEM_C2MISR_MISF3 HSEM_C2MISR_MISF3_Msk

#define	HSEM_C2MISR_MISF4_Pos (4U)

#define	HSEM_C2MISR_MISF4_Msk (0x1UL << HSEM_C2MISR_MISF4_Pos)

#define	HSEM_C2MISR_MISF4 HSEM_C2MISR_MISF4_Msk

#define	HSEM_C2MISR_MISF5_Pos (5U)

#define	HSEM_C2MISR_MISF5_Msk (0x1UL << HSEM_C2MISR_MISF5_Pos)

#define	HSEM_C2MISR_MISF5 HSEM_C2MISR_MISF5_Msk

#define	HSEM_C2MISR_MISF6_Pos (6U)

#define	HSEM_C2MISR_MISF6_Msk (0x1UL << HSEM_C2MISR_MISF6_Pos)

#define	HSEM_C2MISR_MISF6 HSEM_C2MISR_MISF6_Msk

#define	HSEM_C2MISR_MISF7_Pos (7U)

#define	HSEM_C2MISR_MISF7_Msk (0x1UL << HSEM_C2MISR_MISF7_Pos)

#define	HSEM_C2MISR_MISF7 HSEM_C2MISR_MISF7_Msk

#define	HSEM_C2MISR_MISF8_Pos (8U)

#define	HSEM_C2MISR_MISF8_Msk (0x1UL << HSEM_C2MISR_MISF8_Pos)

#define	HSEM_C2MISR_MISF8 HSEM_C2MISR_MISF8_Msk

#define	HSEM_C2MISR_MISF9_Pos (9U)

#define	HSEM_C2MISR_MISF9_Msk (0x1UL << HSEM_C2MISR_MISF9_Pos)

#define	HSEM_C2MISR_MISF9 HSEM_C2MISR_MISF9_Msk

#define	HSEM_C2MISR_MISF10_Pos (10U)

#define	HSEM_C2MISR_MISF10_Msk (0x1UL << HSEM_C2MISR_MISF10_Pos)

#define	HSEM_C2MISR_MISF10 HSEM_C2MISR_MISF10_Msk

#define	HSEM_C2MISR_MISF11_Pos (11U)

#define	HSEM_C2MISR_MISF11_Msk (0x1UL << HSEM_C2MISR_MISF11_Pos)

#define	HSEM_C2MISR_MISF11 HSEM_C2MISR_MISF11_Msk

#define	HSEM_C2MISR_MISF12_Pos (12U)

#define	HSEM_C2MISR_MISF12_Msk (0x1UL << HSEM_C2MISR_MISF12_Pos)

#define	HSEM_C2MISR_MISF12 HSEM_C2MISR_MISF12_Msk

#define	HSEM_C2MISR_MISF13_Pos (13U)

#define	HSEM_C2MISR_MISF13_Msk (0x1UL << HSEM_C2MISR_MISF13_Pos)

#define	HSEM_C2MISR_MISF13 HSEM_C2MISR_MISF13_Msk

#define	HSEM_C2MISR_MISF14_Pos (14U)

#define	HSEM_C2MISR_MISF14_Msk (0x1UL << HSEM_C2MISR_MISF14_Pos)

#define	HSEM_C2MISR_MISF14 HSEM_C2MISR_MISF14_Msk

#define	HSEM_C2MISR_MISF15_Pos (15U)

#define	HSEM_C2MISR_MISF15_Msk (0x1UL << HSEM_C2MISR_MISF15_Pos)

#define	HSEM_C2MISR_MISF15 HSEM_C2MISR_MISF15_Msk

#define	HSEM_CR_COREID_Pos (8U)

#define	HSEM_CR_COREID_Msk (0xFUL << HSEM_CR_COREID_Pos)

#define	HSEM_CR_COREID HSEM_CR_COREID_Msk

#define	HSEM_CR_COREID_CPU1 (0x4U << HSEM_CR_COREID_Pos)

#define	HSEM_CR_COREID_CPU2 (0x8U << HSEM_CR_COREID_Pos)

#define	HSEM_CR_COREID_CURRENT HSEM_CR_COREID_CPU1

#define	HSEM_CR_KEY_Pos (16U)

#define	HSEM_CR_KEY_Msk (0xFFFFUL << HSEM_CR_KEY_Pos)

#define	HSEM_CR_KEY HSEM_CR_KEY_Msk

#define	HSEM_KEYR_KEY_Pos (16U)

#define	HSEM_KEYR_KEY_Msk (0xFFFFUL << HSEM_KEYR_KEY_Pos)

#define	HSEM_KEYR_KEY HSEM_KEYR_KEY_Msk

#define	PKA_CR_EN_Pos (0U)

#define	PKA_CR_EN_Msk (0x1UL << PKA_CR_EN_Pos)

#define	PKA_CR_EN PKA_CR_EN_Msk

#define	PKA_CR_START_Pos (1U)

#define	PKA_CR_START_Msk (0x1UL << PKA_CR_START_Pos)

#define	PKA_CR_START PKA_CR_START_Msk

#define	PKA_CR_MODE_Pos (8U)

#define	PKA_CR_MODE_Msk (0x3FUL << PKA_CR_MODE_Pos)

#define	PKA_CR_MODE PKA_CR_MODE_Msk

#define	PKA_CR_MODE_0 (0x01UL << PKA_CR_MODE_Pos)

#define	PKA_CR_MODE_1 (0x02UL << PKA_CR_MODE_Pos)

#define	PKA_CR_MODE_2 (0x04UL << PKA_CR_MODE_Pos)

#define	PKA_CR_MODE_3 (0x08UL << PKA_CR_MODE_Pos)

#define	PKA_CR_MODE_4 (0x10UL << PKA_CR_MODE_Pos)

#define	PKA_CR_MODE_5 (0x20UL << PKA_CR_MODE_Pos)

#define	PKA_CR_PROCENDIE_Pos (17U)

#define	PKA_CR_PROCENDIE_Msk (0x1UL << PKA_CR_PROCENDIE_Pos)

#define	PKA_CR_PROCENDIE PKA_CR_PROCENDIE_Msk

#define	PKA_CR_RAMERRIE_Pos (19U)

#define	PKA_CR_RAMERRIE_Msk (0x1UL << PKA_CR_RAMERRIE_Pos)

#define	PKA_CR_RAMERRIE PKA_CR_RAMERRIE_Msk

#define	PKA_CR_ADDRERRIE_Pos (20U)

#define	PKA_CR_ADDRERRIE_Msk (0x1UL << PKA_CR_ADDRERRIE_Pos)

#define	PKA_CR_ADDRERRIE PKA_CR_ADDRERRIE_Msk

#define	PKA_SR_BUSY_Pos (16U)

#define	PKA_SR_BUSY_Msk (0x1UL << PKA_SR_BUSY_Pos)

#define	PKA_SR_BUSY PKA_SR_BUSY_Msk

#define	PKA_SR_PROCENDF_Pos (17U)

#define	PKA_SR_PROCENDF_Msk (0x1UL << PKA_SR_PROCENDF_Pos)

#define	PKA_SR_PROCENDF PKA_SR_PROCENDF_Msk

#define	PKA_SR_RAMERRF_Pos (19U)

#define	PKA_SR_RAMERRF_Msk (0x1UL << PKA_SR_RAMERRF_Pos)

#define	PKA_SR_RAMERRF PKA_SR_RAMERRF_Msk

#define	PKA_SR_ADDRERRF_Pos (20U)

#define	PKA_SR_ADDRERRF_Msk (0x1UL << PKA_SR_ADDRERRF_Pos)

#define	PKA_SR_ADDRERRF PKA_SR_ADDRERRF_Msk

#define	PKA_CLRFR_PROCENDFC_Pos (17U)

#define	PKA_CLRFR_PROCENDFC_Msk (0x1UL << PKA_CLRFR_PROCENDFC_Pos)

#define	PKA_CLRFR_PROCENDFC PKA_CLRFR_PROCENDFC_Msk

#define	PKA_CLRFR_RAMERRFC_Pos (19U)

#define	PKA_CLRFR_RAMERRFC_Msk (0x1UL << PKA_CLRFR_RAMERRFC_Pos)

#define	PKA_CLRFR_RAMERRFC PKA_CLRFR_RAMERRFC_Msk

#define	PKA_CLRFR_ADDRERRFC_Pos (20U)

#define	PKA_CLRFR_ADDRERRFC_Msk (0x1UL << PKA_CLRFR_ADDRERRFC_Pos)

#define	PKA_CLRFR_ADDRERRFC PKA_CLRFR_ADDRERRFC_Msk

#define	PKA_RAM_OFFSET 0x400U

#define	PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2)

#define	PKA_MONTGOMERY_PARAM_IN_MODULUS ((0xD5CU - PKA_RAM_OFFSET)>>2)

#define	PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x594U - PKA_RAM_OFFSET)>>2)

#define	PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2)

#define	PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2)

#define	PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x594U - PKA_RAM_OFFSET)>>2)

#define	PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0xA44U - PKA_RAM_OFFSET)>>2)

#define	PKA_MODULAR_EXP_IN_EXPONENT ((0xBD0U - PKA_RAM_OFFSET)>>2)

#define	PKA_MODULAR_EXP_IN_MODULUS ((0xD5CU - PKA_RAM_OFFSET)>>2)

#define	PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x594U - PKA_RAM_OFFSET)>>2)

#define	PKA_MODULAR_EXP_OUT_SM_ALGO_ACC1 ((0x724U - PKA_RAM_OFFSET)>>2)

#define	PKA_MODULAR_EXP_OUT_SM_ALGO_ACC2 ((0x8B4U - PKA_RAM_OFFSET)>>2)

#define	PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0xA44U - PKA_RAM_OFFSET)>>2)

#define	PKA_MODULAR_EXP_OUT_SM_ALGO_ACC3 ((0xE3CU - PKA_RAM_OFFSET)>>2)

#define	PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2)

#define	PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2)

#define	PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2)

#define	PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2)

#define	PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2)

#define	PKA_ECC_SCALAR_MUL_IN_MONTGOMERY_PARAM ((0x4B4U - PKA_RAM_OFFSET)>>2)

#define	PKA_ECC_SCALAR_MUL_IN_K ((0x508U - PKA_RAM_OFFSET)>>2)

#define	PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2)

#define	PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2)

#define	PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x55CU - PKA_RAM_OFFSET)>>2)

#define	PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2)

#define	PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_X1 ((0xDE8U - PKA_RAM_OFFSET)>>2)

#define	PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Y1 ((0xE3CU - PKA_RAM_OFFSET)>>2)

#define	PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Z1 ((0xE90U - PKA_RAM_OFFSET)>>2)

#define	PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_X2 ((0xEE4U - PKA_RAM_OFFSET)>>2)

#define	PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Y2 ((0xF38U - PKA_RAM_OFFSET)>>2)

#define	PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Z2 ((0xF8CU - PKA_RAM_OFFSET)>>2)

#define	PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2)

#define	PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2)

#define	PKA_POINT_CHECK_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2)

#define	PKA_POINT_CHECK_IN_B_COEFF ((0x7FCU - PKA_RAM_OFFSET)>>2)

#define	PKA_POINT_CHECK_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2)

#define	PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2)

#define	PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2)

#define	PKA_POINT_CHECK_OUT_ERROR ((0x400U - PKA_RAM_OFFSET)>>2)

#define	PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2)

#define	PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2)

#define	PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2)

#define	PKA_ECDSA_SIGN_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2)

#define	PKA_ECDSA_SIGN_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2)

#define	PKA_ECDSA_SIGN_IN_K ((0x508U - PKA_RAM_OFFSET)>>2)

#define	PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2)

#define	PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2)

#define	PKA_ECDSA_SIGN_IN_HASH_E ((0xDE8U - PKA_RAM_OFFSET)>>2)

#define	PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0xE3CU - PKA_RAM_OFFSET)>>2)

#define	PKA_ECDSA_SIGN_IN_ORDER_N ((0xE94U - PKA_RAM_OFFSET)>>2)

#define	PKA_ECDSA_SIGN_OUT_ERROR ((0xEE8U - PKA_RAM_OFFSET)>>2)

#define	PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x700U - PKA_RAM_OFFSET)>>2)

#define	PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x754U - PKA_RAM_OFFSET)>>2)

#define	PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x103CU - PKA_RAM_OFFSET)>>2)

#define	PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1090U - PKA_RAM_OFFSET)>>2)

#define	PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2)

#define	PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x4B4U - PKA_RAM_OFFSET)>>2)

#define	PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x45CU - PKA_RAM_OFFSET)>>2)

#define	PKA_ECDSA_VERIF_IN_A_COEFF ((0x460U - PKA_RAM_OFFSET)>>2)

#define	PKA_ECDSA_VERIF_IN_MOD_GF ((0x4B8U - PKA_RAM_OFFSET)>>2)

#define	PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x5E8U - PKA_RAM_OFFSET)>>2)

#define	PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x63CU - PKA_RAM_OFFSET)>>2)

#define	PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0xF40U - PKA_RAM_OFFSET)>>2)

#define	PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0xF94U - PKA_RAM_OFFSET)>>2)

#define	PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x1098U - PKA_RAM_OFFSET)>>2)

#define	PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0xA44U - PKA_RAM_OFFSET)>>2)

#define	PKA_ECDSA_VERIF_IN_HASH_E ((0xFE8U - PKA_RAM_OFFSET)>>2)

#define	PKA_ECDSA_VERIF_IN_ORDER_N ((0xD5CU - PKA_RAM_OFFSET)>>2)

#define	PKA_ECDSA_VERIF_OUT_RESULT ((0x5B0U - PKA_RAM_OFFSET)>>2)

#define	PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2)

#define	PKA_RSA_CRT_EXP_IN_DP_CRT ((0x65CU - PKA_RAM_OFFSET)>>2)

#define	PKA_RSA_CRT_EXP_IN_DQ_CRT ((0xBD0U - PKA_RAM_OFFSET)>>2)

#define	PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x7ECU - PKA_RAM_OFFSET)>>2)

#define	PKA_RSA_CRT_EXP_IN_PRIME_P ((0x97CU - PKA_RAM_OFFSET)>>2)

#define	PKA_RSA_CRT_EXP_IN_PRIME_Q ((0xD5CU - PKA_RAM_OFFSET)>>2)

#define	PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0xEECU - PKA_RAM_OFFSET)>>2)

#define	PKA_RSA_CRT_EXP_OUT_RESULT ((0x724U - PKA_RAM_OFFSET)>>2)

#define	PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x400U - PKA_RAM_OFFSET)>>2)

#define	PKA_MODULAR_REDUC_IN_OPERAND ((0x8B4U - PKA_RAM_OFFSET)>>2)

#define	PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x404U - PKA_RAM_OFFSET)>>2)

#define	PKA_MODULAR_REDUC_IN_MODULUS ((0xA44U - PKA_RAM_OFFSET)>>2)

#define	PKA_MODULAR_REDUC_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2)

#define	PKA_ARITHMETIC_ADD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2)

#define	PKA_ARITHMETIC_ADD_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2)

#define	PKA_ARITHMETIC_ADD_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2)

#define	PKA_ARITHMETIC_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2)

#define	PKA_ARITHMETIC_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2)

#define	PKA_ARITHMETIC_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2)

#define	PKA_ARITHMETIC_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2)

#define	PKA_ARITHMETIC_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2)

#define	PKA_ARITHMETIC_MUL_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2)

#define	PKA_ARITHMETIC_MUL_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2)

#define	PKA_ARITHMETIC_MUL_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2)

#define	PKA_ARITHMETIC_MUL_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2)

#define	PKA_COMPARISON_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2)

#define	PKA_COMPARISON_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2)

#define	PKA_COMPARISON_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2)

#define	PKA_COMPARISON_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2)

#define	PKA_MODULAR_ADD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2)

#define	PKA_MODULAR_ADD_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2)

#define	PKA_MODULAR_ADD_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2)

#define	PKA_MODULAR_ADD_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2)

#define	PKA_MODULAR_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2)

#define	PKA_MODULAR_INV_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2)

#define	PKA_MODULAR_INV_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2)

#define	PKA_MODULAR_INV_IN_OP2_MOD ((0xA44U - PKA_RAM_OFFSET)>>2)

#define	PKA_MODULAR_INV_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2)

#define	PKA_MODULAR_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2)

#define	PKA_MODULAR_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2)

#define	PKA_MODULAR_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2)

#define	PKA_MODULAR_SUB_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2)

#define	PKA_MODULAR_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2)

#define	PKA_MONTGOMERY_MUL_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2)

#define	PKA_MONTGOMERY_MUL_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2)

#define	PKA_MONTGOMERY_MUL_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2)

#define	PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2)

#define	PKA_MONTGOMERY_MUL_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2)

#define	PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2)

#define	PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2)

#define	PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2)

#define	PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0xD5CU - PKA_RAM_OFFSET)>>2)

#define	PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2)

#define	PWR_CR1_LPMS_Pos (0U)

#define	PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos)

#define	PWR_CR1_LPMS PWR_CR1_LPMS_Msk

#define	PWR_CR1_LPMS_0 (0x1UL << PWR_CR1_LPMS_Pos)

#define	PWR_CR1_LPMS_1 (0x2UL << PWR_CR1_LPMS_Pos)

#define	PWR_CR1_LPMS_2 (0x4UL << PWR_CR1_LPMS_Pos)

#define	PWR_CR1_SUBGHZSPINSSSEL_Pos (3U)

#define	PWR_CR1_SUBGHZSPINSSSEL_Msk (0x1UL << PWR_CR1_SUBGHZSPINSSSEL_Pos)

#define	PWR_CR1_SUBGHZSPINSSSEL PWR_CR1_SUBGHZSPINSSSEL_Msk

#define	PWR_CR1_FPDR_Pos (4U)

#define	PWR_CR1_FPDR_Msk (0x1UL << PWR_CR1_FPDR_Pos)

#define	PWR_CR1_FPDR PWR_CR1_FPDR_Msk

#define	PWR_CR1_FPDS_Pos (5U)

#define	PWR_CR1_FPDS_Msk (0x1UL << PWR_CR1_FPDS_Pos)

#define	PWR_CR1_FPDS PWR_CR1_FPDS_Msk

#define	PWR_CR1_DBP_Pos (8U)

#define	PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos)

#define	PWR_CR1_DBP PWR_CR1_DBP_Msk

#define	PWR_CR1_VOS_Pos (9U)

#define	PWR_CR1_VOS_Msk (0x3UL << PWR_CR1_VOS_Pos)

#define	PWR_CR1_VOS PWR_CR1_VOS_Msk

#define	PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_Pos)

#define	PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_Pos)

#define	PWR_CR1_LPR_Pos (14U)

#define	PWR_CR1_LPR_Msk (0x1UL << PWR_CR1_LPR_Pos)

#define	PWR_CR1_LPR PWR_CR1_LPR_Msk

#define	PWR_CR2_PVDE_Pos (0U)

#define	PWR_CR2_PVDE_Msk (0x1UL << PWR_CR2_PVDE_Pos)

#define	PWR_CR2_PVDE PWR_CR2_PVDE_Msk

#define	PWR_CR2_PLS_Pos (1U)

#define	PWR_CR2_PLS_Msk (0x7UL << PWR_CR2_PLS_Pos)

#define	PWR_CR2_PLS PWR_CR2_PLS_Msk

#define	PWR_CR2_PLS_0 (0x1UL << PWR_CR2_PLS_Pos)

#define	PWR_CR2_PLS_1 (0x2UL << PWR_CR2_PLS_Pos)

#define	PWR_CR2_PLS_2 (0x4UL << PWR_CR2_PLS_Pos)

#define	PWR_CR2_PVME3_Pos (6U)

#define	PWR_CR2_PVME3_Msk (0x1UL << PWR_CR2_PVME3_Pos)

#define	PWR_CR2_PVME3 PWR_CR2_PVME3_Msk

#define	PWR_CR3_EWUP_Pos (0U)

#define	PWR_CR3_EWUP_Msk (0x07UL << PWR_CR3_EWUP_Pos)

#define	PWR_CR3_EWUP PWR_CR3_EWUP_Msk

#define	PWR_CR3_EWUP1_Pos (0U)

#define	PWR_CR3_EWUP1_Msk (0x1UL << PWR_CR3_EWUP1_Pos)

#define	PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk

#define	PWR_CR3_EWUP2_Pos (1U)

#define	PWR_CR3_EWUP2_Msk (0x1UL << PWR_CR3_EWUP2_Pos)

#define	PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk

#define	PWR_CR3_EWUP3_Pos (2U)

#define	PWR_CR3_EWUP3_Msk (0x1UL << PWR_CR3_EWUP3_Pos)

#define	PWR_CR3_EWUP3 PWR_CR3_EWUP3_Msk

#define	PWR_CR3_ULPEN_Pos (7U)

#define	PWR_CR3_ULPEN_Msk (0x1UL << PWR_CR3_ULPEN_Pos)

#define	PWR_CR3_ULPEN PWR_CR3_ULPEN_Msk

#define	PWR_CR3_EWPVD_Pos (8U)

#define	PWR_CR3_EWPVD_Msk (0x1UL << PWR_CR3_EWPVD_Pos)

#define	PWR_CR3_EWPVD PWR_CR3_EWPVD_Msk

#define	PWR_CR3_RRS_Pos (9U)

#define	PWR_CR3_RRS_Msk (0x1UL << PWR_CR3_RRS_Pos)

#define	PWR_CR3_RRS PWR_CR3_RRS_Msk

#define	PWR_CR3_APC_Pos (10U)

#define	PWR_CR3_APC_Msk (0x1UL << PWR_CR3_APC_Pos)

#define	PWR_CR3_APC PWR_CR3_APC_Msk

#define	PWR_CR3_EWRFBUSY_Pos (11U)

#define	PWR_CR3_EWRFBUSY_Msk (0x1UL << PWR_CR3_EWRFBUSY_Pos)

#define	PWR_CR3_EWRFBUSY PWR_CR3_EWRFBUSY_Msk

#define	PWR_CR3_EWRFIRQ_Pos (13U)

#define	PWR_CR3_EWRFIRQ_Msk (0x1UL << PWR_CR3_EWRFIRQ_Pos)

#define	PWR_CR3_EWRFIRQ PWR_CR3_EWRFIRQ_Msk

#define	PWR_CR3_EC2H_Pos (14U)

#define	PWR_CR3_EC2H_Msk (0x1UL << PWR_CR3_EC2H_Pos)

#define	PWR_CR3_EC2H PWR_CR3_EC2H_Msk

#define	PWR_CR3_EIWUL_Pos (15U)

#define	PWR_CR3_EIWUL_Msk (0x1UL << PWR_CR3_EIWUL_Pos)

#define	PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk

#define	PWR_CR4_WP1_Pos (0U)

#define	PWR_CR4_WP1_Msk (0x1UL << PWR_CR4_WP1_Pos)

#define	PWR_CR4_WP1 PWR_CR4_WP1_Msk

#define	PWR_CR4_WP2_Pos (1U)

#define	PWR_CR4_WP2_Msk (0x1UL << PWR_CR4_WP2_Pos)

#define	PWR_CR4_WP2 PWR_CR4_WP2_Msk

#define	PWR_CR4_WP3_Pos (2U)

#define	PWR_CR4_WP3_Msk (0x1UL << PWR_CR4_WP3_Pos)

#define	PWR_CR4_WP3 PWR_CR4_WP3_Msk

#define	PWR_CR4_VBE_Pos (8U)

#define	PWR_CR4_VBE_Msk (0x1UL << PWR_CR4_VBE_Pos)

#define	PWR_CR4_VBE PWR_CR4_VBE_Msk

#define	PWR_CR4_VBRS_Pos (9U)

#define	PWR_CR4_VBRS_Msk (0x1UL << PWR_CR4_VBRS_Pos)

#define	PWR_CR4_VBRS PWR_CR4_VBRS_Msk

#define	PWR_CR4_WRFBUSYP_Pos (11U)

#define	PWR_CR4_WRFBUSYP_Msk (0x1UL << PWR_CR4_WRFBUSYP_Pos)

#define	PWR_CR4_WRFBUSYP PWR_CR4_WRFBUSYP_Msk

#define	PWR_CR4_C2BOOT_Pos (15U)

#define	PWR_CR4_C2BOOT_Msk (0x1UL << PWR_CR4_C2BOOT_Pos)

#define	PWR_CR4_C2BOOT PWR_CR4_C2BOOT_Msk

#define	PWR_SR1_WUF_Pos (0U)

#define	PWR_SR1_WUF_Msk (0x1FUL << PWR_SR1_WUF_Pos)

#define	PWR_SR1_WUF PWR_SR1_WUF_Msk

#define	PWR_SR1_WUF1_Pos (0U)

#define	PWR_SR1_WUF1_Msk (0x1UL << PWR_SR1_WUF1_Pos)

#define	PWR_SR1_WUF1 PWR_SR1_WUF1_Msk

#define	PWR_SR1_WUF2_Pos (1U)

#define	PWR_SR1_WUF2_Msk (0x1UL << PWR_SR1_WUF2_Pos)

#define	PWR_SR1_WUF2 PWR_SR1_WUF2_Msk

#define	PWR_SR1_WUF3_Pos (2U)

#define	PWR_SR1_WUF3_Msk (0x1UL << PWR_SR1_WUF3_Pos)

#define	PWR_SR1_WUF3 PWR_SR1_WUF3_Msk

#define	PWR_SR1_WPVDF_Pos (8U)

#define	PWR_SR1_WPVDF_Msk (0x1UL << PWR_SR1_WPVDF_Pos)

#define	PWR_SR1_WPVDF PWR_SR1_WPVDF_Msk

#define	PWR_SR1_WRFBUSYF_Pos (11U)

#define	PWR_SR1_WRFBUSYF_Msk (0x1UL << PWR_SR1_WRFBUSYF_Pos)

#define	PWR_SR1_WRFBUSYF PWR_SR1_WRFBUSYF_Msk

#define	PWR_SR1_C2HF_Pos (14U)

#define	PWR_SR1_C2HF_Msk (0x1UL << PWR_SR1_C2HF_Pos)

#define	PWR_SR1_C2HF PWR_SR1_C2HF_Msk

#define	PWR_SR1_WUFI_Pos (15U)

#define	PWR_SR1_WUFI_Msk (0x1UL << PWR_SR1_WUFI_Pos)

#define	PWR_SR1_WUFI PWR_SR1_WUFI_Msk

#define	PWR_SR2_C2BOOTS_Pos (0U)

#define	PWR_SR2_C2BOOTS_Msk (0x1UL << PWR_SR2_C2BOOTS_Pos)

#define	PWR_SR2_C2BOOTS PWR_SR2_C2BOOTS_Msk

#define	PWR_SR2_RFBUSYS_Pos (1U)

#define	PWR_SR2_RFBUSYS_Msk (0x1UL << PWR_SR2_RFBUSYS_Pos)

#define	PWR_SR2_RFBUSYS PWR_SR2_RFBUSYS_Msk

#define	PWR_SR2_RFBUSYMS_Pos (2U)

#define	PWR_SR2_RFBUSYMS_Msk (0x1UL << PWR_SR2_RFBUSYMS_Pos)

#define	PWR_SR2_RFBUSYMS PWR_SR2_RFBUSYMS_Msk

#define	PWR_SR2_SMPSRDY_Pos (3U)

#define	PWR_SR2_SMPSRDY_Msk (0x1UL << PWR_SR2_SMPSRDY_Pos)

#define	PWR_SR2_SMPSRDY PWR_SR2_SMPSRDY_Msk

#define	PWR_SR2_LDORDY_Pos (4U)

#define	PWR_SR2_LDORDY_Msk (0x1UL << PWR_SR2_LDORDY_Pos)

#define	PWR_SR2_LDORDY PWR_SR2_LDORDY_Msk

#define	PWR_SR2_RFEOLF_Pos (5U)

#define	PWR_SR2_RFEOLF_Msk (0x1UL << PWR_SR2_RFEOLF_Pos)

#define	PWR_SR2_RFEOLF PWR_SR2_RFEOLF_Msk

#define	PWR_SR2_REGMRS_Pos (6U)

#define	PWR_SR2_REGMRS_Msk (0x1UL << PWR_SR2_REGMRS_Pos)

#define	PWR_SR2_REGMRS PWR_SR2_REGMRS_Msk

#define	PWR_SR2_FLASHRDY_Pos (7U)

#define	PWR_SR2_FLASHRDY_Msk (0x1UL << PWR_SR2_FLASHRDY_Pos)

#define	PWR_SR2_FLASHRDY PWR_SR2_FLASHRDY_Msk

#define	PWR_SR2_REGLPS_Pos (8U)

#define	PWR_SR2_REGLPS_Msk (0x1UL << PWR_SR2_REGLPS_Pos)

#define	PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk

#define	PWR_SR2_REGLPF_Pos (9U)

#define	PWR_SR2_REGLPF_Msk (0x1UL << PWR_SR2_REGLPF_Pos)

#define	PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk

#define	PWR_SR2_VOSF_Pos (10U)

#define	PWR_SR2_VOSF_Msk (0x1UL << PWR_SR2_VOSF_Pos)

#define	PWR_SR2_VOSF PWR_SR2_VOSF_Msk

#define	PWR_SR2_PVDO_Pos (11U)

#define	PWR_SR2_PVDO_Msk (0x1UL << PWR_SR2_PVDO_Pos)

#define	PWR_SR2_PVDO PWR_SR2_PVDO_Msk

#define	PWR_SR2_PVMO3_Pos (14U)

#define	PWR_SR2_PVMO3_Msk (0x1UL << PWR_SR2_PVMO3_Pos)

#define	PWR_SR2_PVMO3 PWR_SR2_PVMO3_Msk

#define	PWR_SCR_CWUF_Pos (0U)

#define	PWR_SCR_CWUF_Msk (0x7UL << PWR_SCR_CWUF_Pos)

#define	PWR_SCR_CWUF PWR_SCR_CWUF_Msk

#define	PWR_SCR_CWUF1_Pos (0U)

#define	PWR_SCR_CWUF1_Msk (0x1UL << PWR_SCR_CWUF1_Pos)

#define	PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk

#define	PWR_SCR_CWUF2_Pos (1U)

#define	PWR_SCR_CWUF2_Msk (0x1UL << PWR_SCR_CWUF2_Pos)

#define	PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk

#define	PWR_SCR_CWUF3_Pos (2U)

#define	PWR_SCR_CWUF3_Msk (0x1UL << PWR_SCR_CWUF3_Pos)

#define	PWR_SCR_CWUF3 PWR_SCR_CWUF3_Msk

#define	PWR_SCR_CWPVDF_Pos (8U)

#define	PWR_SCR_CWPVDF_Msk (0x1UL << PWR_SCR_CWPVDF_Pos)

#define	PWR_SCR_CWPVDF PWR_SCR_CWPVDF_Msk

#define	PWR_SCR_CWRFBUSYF_Pos (11U)

#define	PWR_SCR_CWRFBUSYF_Msk (0x1UL << PWR_SCR_CWRFBUSYF_Pos)

#define	PWR_SCR_CWRFBUSYF PWR_SCR_CWRFBUSYF_Msk

#define	PWR_SCR_CC2HF_Pos (14U)

#define	PWR_SCR_CC2HF_Msk (0x1UL << PWR_SCR_CC2HF_Pos)

#define	PWR_SCR_CC2HF PWR_SCR_CC2HF_Msk

#define	PWR_CR5_RFEOLEN_Pos (14U)

#define	PWR_CR5_RFEOLEN_Msk (0x1UL << PWR_CR5_RFEOLEN_Pos)

#define	PWR_CR5_RFEOLEN PWR_CR5_RFEOLEN_Msk

#define	PWR_CR5_SMPSEN_Pos (15U)

#define	PWR_CR5_SMPSEN_Msk (0x1UL << PWR_CR5_SMPSEN_Pos)

#define	PWR_CR5_SMPSEN PWR_CR5_SMPSEN_Msk

#define	PWR_PUCRA_PA0_Pos (0U)

#define	PWR_PUCRA_PA0_Msk (0x1UL << PWR_PUCRA_PA0_Pos)

#define	PWR_PUCRA_PA0 PWR_PUCRA_PA0_Msk

#define	PWR_PUCRA_PA1_Pos (1U)

#define	PWR_PUCRA_PA1_Msk (0x1UL << PWR_PUCRA_PA1_Pos)

#define	PWR_PUCRA_PA1 PWR_PUCRA_PA1_Msk

#define	PWR_PUCRA_PA2_Pos (2U)

#define	PWR_PUCRA_PA2_Msk (0x1UL << PWR_PUCRA_PA2_Pos)

#define	PWR_PUCRA_PA2 PWR_PUCRA_PA2_Msk

#define	PWR_PUCRA_PA3_Pos (3U)

#define	PWR_PUCRA_PA3_Msk (0x1UL << PWR_PUCRA_PA3_Pos)

#define	PWR_PUCRA_PA3 PWR_PUCRA_PA3_Msk

#define	PWR_PUCRA_PA4_Pos (4U)

#define	PWR_PUCRA_PA4_Msk (0x1UL << PWR_PUCRA_PA4_Pos)

#define	PWR_PUCRA_PA4 PWR_PUCRA_PA4_Msk

#define	PWR_PUCRA_PA5_Pos (5U)

#define	PWR_PUCRA_PA5_Msk (0x1UL << PWR_PUCRA_PA5_Pos)

#define	PWR_PUCRA_PA5 PWR_PUCRA_PA5_Msk

#define	PWR_PUCRA_PA6_Pos (6U)

#define	PWR_PUCRA_PA6_Msk (0x1UL << PWR_PUCRA_PA6_Pos)

#define	PWR_PUCRA_PA6 PWR_PUCRA_PA6_Msk

#define	PWR_PUCRA_PA7_Pos (7U)

#define	PWR_PUCRA_PA7_Msk (0x1UL << PWR_PUCRA_PA7_Pos)

#define	PWR_PUCRA_PA7 PWR_PUCRA_PA7_Msk

#define	PWR_PUCRA_PA8_Pos (8U)

#define	PWR_PUCRA_PA8_Msk (0x1UL << PWR_PUCRA_PA8_Pos)

#define	PWR_PUCRA_PA8 PWR_PUCRA_PA8_Msk

#define	PWR_PUCRA_PA9_Pos (9U)

#define	PWR_PUCRA_PA9_Msk (0x1UL << PWR_PUCRA_PA9_Pos)

#define	PWR_PUCRA_PA9 PWR_PUCRA_PA9_Msk

#define	PWR_PUCRA_PA10_Pos (10U)

#define	PWR_PUCRA_PA10_Msk (0x1UL << PWR_PUCRA_PA10_Pos)

#define	PWR_PUCRA_PA10 PWR_PUCRA_PA10_Msk

#define	PWR_PUCRA_PA11_Pos (11U)

#define	PWR_PUCRA_PA11_Msk (0x1UL << PWR_PUCRA_PA11_Pos)

#define	PWR_PUCRA_PA11 PWR_PUCRA_PA11_Msk

#define	PWR_PUCRA_PA12_Pos (12U)

#define	PWR_PUCRA_PA12_Msk (0x1UL << PWR_PUCRA_PA12_Pos)

#define	PWR_PUCRA_PA12 PWR_PUCRA_PA12_Msk

#define	PWR_PUCRA_PA13_Pos (13U)

#define	PWR_PUCRA_PA13_Msk (0x1UL << PWR_PUCRA_PA13_Pos)

#define	PWR_PUCRA_PA13 PWR_PUCRA_PA13_Msk

#define	PWR_PUCRA_PA14_Pos (14U)

#define	PWR_PUCRA_PA14_Msk (0x1UL << PWR_PUCRA_PA14_Pos)

#define	PWR_PUCRA_PA14 PWR_PUCRA_PA14_Msk

#define	PWR_PUCRA_PA15_Pos (15U)

#define	PWR_PUCRA_PA15_Msk (0x1UL << PWR_PUCRA_PA15_Pos)

#define	PWR_PUCRA_PA15 PWR_PUCRA_PA15_Msk

#define	PWR_PDCRA_PA0_Pos (0U)

#define	PWR_PDCRA_PA0_Msk (0x1UL << PWR_PDCRA_PA0_Pos)

#define	PWR_PDCRA_PA0 PWR_PDCRA_PA0_Msk

#define	PWR_PDCRA_PA1_Pos (1U)

#define	PWR_PDCRA_PA1_Msk (0x1UL << PWR_PDCRA_PA1_Pos)

#define	PWR_PDCRA_PA1 PWR_PDCRA_PA1_Msk

#define	PWR_PDCRA_PA2_Pos (2U)

#define	PWR_PDCRA_PA2_Msk (0x1UL << PWR_PDCRA_PA2_Pos)

#define	PWR_PDCRA_PA2 PWR_PDCRA_PA2_Msk

#define	PWR_PDCRA_PA3_Pos (3U)

#define	PWR_PDCRA_PA3_Msk (0x1UL << PWR_PDCRA_PA3_Pos)

#define	PWR_PDCRA_PA3 PWR_PDCRA_PA3_Msk

#define	PWR_PDCRA_PA4_Pos (4U)

#define	PWR_PDCRA_PA4_Msk (0x1UL << PWR_PDCRA_PA4_Pos)

#define	PWR_PDCRA_PA4 PWR_PDCRA_PA4_Msk

#define	PWR_PDCRA_PA5_Pos (5U)

#define	PWR_PDCRA_PA5_Msk (0x1UL << PWR_PDCRA_PA5_Pos)

#define	PWR_PDCRA_PA5 PWR_PDCRA_PA5_Msk

#define	PWR_PDCRA_PA6_Pos (6U)

#define	PWR_PDCRA_PA6_Msk (0x1UL << PWR_PDCRA_PA6_Pos)

#define	PWR_PDCRA_PA6 PWR_PDCRA_PA6_Msk

#define	PWR_PDCRA_PA7_Pos (7U)

#define	PWR_PDCRA_PA7_Msk (0x1UL << PWR_PDCRA_PA7_Pos)

#define	PWR_PDCRA_PA7 PWR_PDCRA_PA7_Msk

#define	PWR_PDCRA_PA8_Pos (8U)

#define	PWR_PDCRA_PA8_Msk (0x1UL << PWR_PDCRA_PA8_Pos)

#define	PWR_PDCRA_PA8 PWR_PDCRA_PA8_Msk

#define	PWR_PDCRA_PA9_Pos (9U)

#define	PWR_PDCRA_PA9_Msk (0x1UL << PWR_PDCRA_PA9_Pos)

#define	PWR_PDCRA_PA9 PWR_PDCRA_PA9_Msk

#define	PWR_PDCRA_PA10_Pos (10U)

#define	PWR_PDCRA_PA10_Msk (0x1UL << PWR_PDCRA_PA10_Pos)

#define	PWR_PDCRA_PA10 PWR_PDCRA_PA10_Msk

#define	PWR_PDCRA_PA11_Pos (11U)

#define	PWR_PDCRA_PA11_Msk (0x1UL << PWR_PDCRA_PA11_Pos)

#define	PWR_PDCRA_PA11 PWR_PDCRA_PA11_Msk

#define	PWR_PDCRA_PA12_Pos (12U)

#define	PWR_PDCRA_PA12_Msk (0x1UL << PWR_PDCRA_PA12_Pos)

#define	PWR_PDCRA_PA12 PWR_PDCRA_PA12_Msk

#define	PWR_PDCRA_PA13_Pos (13U)

#define	PWR_PDCRA_PA13_Msk (0x1UL << PWR_PDCRA_PA13_Pos)

#define	PWR_PDCRA_PA13 PWR_PDCRA_PA13_Msk

#define	PWR_PDCRA_PA14_Pos (14U)

#define	PWR_PDCRA_PA14_Msk (0x1UL << PWR_PDCRA_PA14_Pos)

#define	PWR_PDCRA_PA14 PWR_PDCRA_PA14_Msk

#define	PWR_PDCRA_PA15_Pos (15U)

#define	PWR_PDCRA_PA15_Msk (0x1UL << PWR_PDCRA_PA15_Pos)

#define	PWR_PDCRA_PA15 PWR_PDCRA_PA15_Msk

#define	PWR_PUCRB_PB0_Pos (0U)

#define	PWR_PUCRB_PB0_Msk (0x1UL << PWR_PUCRB_PB0_Pos)

#define	PWR_PUCRB_PB0 PWR_PUCRB_PB0_Msk

#define	PWR_PUCRB_PB1_Pos (1U)

#define	PWR_PUCRB_PB1_Msk (0x1UL << PWR_PUCRB_PB1_Pos)

#define	PWR_PUCRB_PB1 PWR_PUCRB_PB1_Msk

#define	PWR_PUCRB_PB2_Pos (2U)

#define	PWR_PUCRB_PB2_Msk (0x1UL << PWR_PUCRB_PB2_Pos)

#define	PWR_PUCRB_PB2 PWR_PUCRB_PB2_Msk

#define	PWR_PUCRB_PB3_Pos (3U)

#define	PWR_PUCRB_PB3_Msk (0x1UL << PWR_PUCRB_PB3_Pos)

#define	PWR_PUCRB_PB3 PWR_PUCRB_PB3_Msk

#define	PWR_PUCRB_PB4_Pos (4U)

#define	PWR_PUCRB_PB4_Msk (0x1UL << PWR_PUCRB_PB4_Pos)

#define	PWR_PUCRB_PB4 PWR_PUCRB_PB4_Msk

#define	PWR_PUCRB_PB5_Pos (5U)

#define	PWR_PUCRB_PB5_Msk (0x1UL << PWR_PUCRB_PB5_Pos)

#define	PWR_PUCRB_PB5 PWR_PUCRB_PB5_Msk

#define	PWR_PUCRB_PB6_Pos (6U)

#define	PWR_PUCRB_PB6_Msk (0x1UL << PWR_PUCRB_PB6_Pos)

#define	PWR_PUCRB_PB6 PWR_PUCRB_PB6_Msk

#define	PWR_PUCRB_PB7_Pos (7U)

#define	PWR_PUCRB_PB7_Msk (0x1UL << PWR_PUCRB_PB7_Pos)

#define	PWR_PUCRB_PB7 PWR_PUCRB_PB7_Msk

#define	PWR_PUCRB_PB8_Pos (8U)

#define	PWR_PUCRB_PB8_Msk (0x1UL << PWR_PUCRB_PB8_Pos)

#define	PWR_PUCRB_PB8 PWR_PUCRB_PB8_Msk

#define	PWR_PUCRB_PB9_Pos (9U)

#define	PWR_PUCRB_PB9_Msk (0x1UL << PWR_PUCRB_PB9_Pos)

#define	PWR_PUCRB_PB9 PWR_PUCRB_PB9_Msk

#define	PWR_PUCRB_PB10_Pos (10U)

#define	PWR_PUCRB_PB10_Msk (0x1UL << PWR_PUCRB_PB10_Pos)

#define	PWR_PUCRB_PB10 PWR_PUCRB_PB10_Msk

#define	PWR_PUCRB_PB11_Pos (11U)

#define	PWR_PUCRB_PB11_Msk (0x1UL << PWR_PUCRB_PB11_Pos)

#define	PWR_PUCRB_PB11 PWR_PUCRB_PB11_Msk

#define	PWR_PUCRB_PB12_Pos (12U)

#define	PWR_PUCRB_PB12_Msk (0x1UL << PWR_PUCRB_PB12_Pos)

#define	PWR_PUCRB_PB12 PWR_PUCRB_PB12_Msk

#define	PWR_PUCRB_PB13_Pos (13U)

#define	PWR_PUCRB_PB13_Msk (0x1UL << PWR_PUCRB_PB13_Pos)

#define	PWR_PUCRB_PB13 PWR_PUCRB_PB13_Msk

#define	PWR_PUCRB_PB14_Pos (14U)

#define	PWR_PUCRB_PB14_Msk (0x1UL << PWR_PUCRB_PB14_Pos)

#define	PWR_PUCRB_PB14 PWR_PUCRB_PB14_Msk

#define	PWR_PUCRB_PB15_Pos (15U)

#define	PWR_PUCRB_PB15_Msk (0x1UL << PWR_PUCRB_PB15_Pos)

#define	PWR_PUCRB_PB15 PWR_PUCRB_PB15_Msk

#define	PWR_PDCRB_PB0_Pos (0U)

#define	PWR_PDCRB_PB0_Msk (0x1UL << PWR_PDCRB_PB0_Pos)

#define	PWR_PDCRB_PB0 PWR_PDCRB_PB0_Msk

#define	PWR_PDCRB_PB1_Pos (1U)

#define	PWR_PDCRB_PB1_Msk (0x1UL << PWR_PDCRB_PB1_Pos)

#define	PWR_PDCRB_PB1 PWR_PDCRB_PB1_Msk

#define	PWR_PDCRB_PB2_Pos (2U)

#define	PWR_PDCRB_PB2_Msk (0x1UL << PWR_PDCRB_PB2_Pos)

#define	PWR_PDCRB_PB2 PWR_PDCRB_PB2_Msk

#define	PWR_PDCRB_PB3_Pos (3U)

#define	PWR_PDCRB_PB3_Msk (0x1UL << PWR_PDCRB_PB3_Pos)

#define	PWR_PDCRB_PB3 PWR_PDCRB_PB3_Msk

#define	PWR_PDCRB_PB4_Pos (4U)

#define	PWR_PDCRB_PB4_Msk (0x1UL << PWR_PDCRB_PB4_Pos)

#define	PWR_PDCRB_PB4 PWR_PDCRB_PB4_Msk

#define	PWR_PDCRB_PB5_Pos (5U)

#define	PWR_PDCRB_PB5_Msk (0x1UL << PWR_PDCRB_PB5_Pos)

#define	PWR_PDCRB_PB5 PWR_PDCRB_PB5_Msk

#define	PWR_PDCRB_PB6_Pos (6U)

#define	PWR_PDCRB_PB6_Msk (0x1UL << PWR_PDCRB_PB6_Pos)

#define	PWR_PDCRB_PB6 PWR_PDCRB_PB6_Msk

#define	PWR_PDCRB_PB7_Pos (7U)

#define	PWR_PDCRB_PB7_Msk (0x1UL << PWR_PDCRB_PB7_Pos)

#define	PWR_PDCRB_PB7 PWR_PDCRB_PB7_Msk

#define	PWR_PDCRB_PB8_Pos (8U)

#define	PWR_PDCRB_PB8_Msk (0x1UL << PWR_PDCRB_PB8_Pos)

#define	PWR_PDCRB_PB8 PWR_PDCRB_PB8_Msk

#define	PWR_PDCRB_PB9_Pos (9U)

#define	PWR_PDCRB_PB9_Msk (0x1UL << PWR_PDCRB_PB9_Pos)

#define	PWR_PDCRB_PB9 PWR_PDCRB_PB9_Msk

#define	PWR_PDCRB_PB10_Pos (10U)

#define	PWR_PDCRB_PB10_Msk (0x1UL << PWR_PDCRB_PB10_Pos)

#define	PWR_PDCRB_PB10 PWR_PDCRB_PB10_Msk

#define	PWR_PDCRB_PB11_Pos (11U)

#define	PWR_PDCRB_PB11_Msk (0x1UL << PWR_PDCRB_PB11_Pos)

#define	PWR_PDCRB_PB11 PWR_PDCRB_PB11_Msk

#define	PWR_PDCRB_PB12_Pos (12U)

#define	PWR_PDCRB_PB12_Msk (0x1UL << PWR_PDCRB_PB12_Pos)

#define	PWR_PDCRB_PB12 PWR_PDCRB_PB12_Msk

#define	PWR_PDCRB_PB13_Pos (13U)

#define	PWR_PDCRB_PB13_Msk (0x1UL << PWR_PDCRB_PB13_Pos)

#define	PWR_PDCRB_PB13 PWR_PDCRB_PB13_Msk

#define	PWR_PDCRB_PB14_Pos (14U)

#define	PWR_PDCRB_PB14_Msk (0x1UL << PWR_PDCRB_PB14_Pos)

#define	PWR_PDCRB_PB14 PWR_PDCRB_PB14_Msk

#define	PWR_PDCRB_PB15_Pos (15U)

#define	PWR_PDCRB_PB15_Msk (0x1UL << PWR_PDCRB_PB15_Pos)

#define	PWR_PDCRB_PB15 PWR_PDCRB_PB15_Msk

#define	PWR_PUCRC_PC0_Pos (0U)

#define	PWR_PUCRC_PC0_Msk (0x1UL << PWR_PUCRC_PC0_Pos)

#define	PWR_PUCRC_PC0 PWR_PUCRC_PC0_Msk

#define	PWR_PUCRC_PC1_Pos (1U)

#define	PWR_PUCRC_PC1_Msk (0x1UL << PWR_PUCRC_PC1_Pos)

#define	PWR_PUCRC_PC1 PWR_PUCRC_PC1_Msk

#define	PWR_PUCRC_PC2_Pos (2U)

#define	PWR_PUCRC_PC2_Msk (0x1UL << PWR_PUCRC_PC2_Pos)

#define	PWR_PUCRC_PC2 PWR_PUCRC_PC2_Msk

#define	PWR_PUCRC_PC3_Pos (3U)

#define	PWR_PUCRC_PC3_Msk (0x1UL << PWR_PUCRC_PC3_Pos)

#define	PWR_PUCRC_PC3 PWR_PUCRC_PC3_Msk

#define	PWR_PUCRC_PC4_Pos (4U)

#define	PWR_PUCRC_PC4_Msk (0x1UL << PWR_PUCRC_PC4_Pos)

#define	PWR_PUCRC_PC4 PWR_PUCRC_PC4_Msk

#define	PWR_PUCRC_PC5_Pos (5U)

#define	PWR_PUCRC_PC5_Msk (0x1UL << PWR_PUCRC_PC5_Pos)

#define	PWR_PUCRC_PC5 PWR_PUCRC_PC5_Msk

#define	PWR_PUCRC_PC6_Pos (6U)

#define	PWR_PUCRC_PC6_Msk (0x1UL << PWR_PUCRC_PC6_Pos)

#define	PWR_PUCRC_PC6 PWR_PUCRC_PC6_Msk

#define	PWR_PUCRC_PC13_Pos (13U)

#define	PWR_PUCRC_PC13_Msk (0x1UL << PWR_PUCRC_PC13_Pos)

#define	PWR_PUCRC_PC13 PWR_PUCRC_PC13_Msk

#define	PWR_PUCRC_PC14_Pos (14U)

#define	PWR_PUCRC_PC14_Msk (0x1UL << PWR_PUCRC_PC14_Pos)

#define	PWR_PUCRC_PC14 PWR_PUCRC_PC14_Msk

#define	PWR_PUCRC_PC15_Pos (15U)

#define	PWR_PUCRC_PC15_Msk (0x1UL << PWR_PUCRC_PC15_Pos)

#define	PWR_PUCRC_PC15 PWR_PUCRC_PC15_Msk

#define	PWR_PDCRC_PC0_Pos (0U)

#define	PWR_PDCRC_PC0_Msk (0x1UL << PWR_PDCRC_PC0_Pos)

#define	PWR_PDCRC_PC0 PWR_PDCRC_PC0_Msk

#define	PWR_PDCRC_PC1_Pos (1U)

#define	PWR_PDCRC_PC1_Msk (0x1UL << PWR_PDCRC_PC1_Pos)

#define	PWR_PDCRC_PC1 PWR_PDCRC_PC1_Msk

#define	PWR_PDCRC_PC2_Pos (2U)

#define	PWR_PDCRC_PC2_Msk (0x1UL << PWR_PDCRC_PC2_Pos)

#define	PWR_PDCRC_PC2 PWR_PDCRC_PC2_Msk

#define	PWR_PDCRC_PC3_Pos (3U)

#define	PWR_PDCRC_PC3_Msk (0x1UL << PWR_PDCRC_PC3_Pos)

#define	PWR_PDCRC_PC3 PWR_PDCRC_PC3_Msk

#define	PWR_PDCRC_PC4_Pos (4U)

#define	PWR_PDCRC_PC4_Msk (0x1UL << PWR_PDCRC_PC4_Pos)

#define	PWR_PDCRC_PC4 PWR_PDCRC_PC4_Msk

#define	PWR_PDCRC_PC5_Pos (5U)

#define	PWR_PDCRC_PC5_Msk (0x1UL << PWR_PDCRC_PC5_Pos)

#define	PWR_PDCRC_PC5 PWR_PDCRC_PC5_Msk

#define	PWR_PDCRC_PC6_Pos (6U)

#define	PWR_PDCRC_PC6_Msk (0x1UL << PWR_PDCRC_PC6_Pos)

#define	PWR_PDCRC_PC6 PWR_PDCRC_PC6_Msk

#define	PWR_PDCRC_PC13_Pos (13U)

#define	PWR_PDCRC_PC13_Msk (0x1UL << PWR_PDCRC_PC13_Pos)

#define	PWR_PDCRC_PC13 PWR_PDCRC_PC13_Msk

#define	PWR_PDCRC_PC14_Pos (14U)

#define	PWR_PDCRC_PC14_Msk (0x1UL << PWR_PDCRC_PC14_Pos)

#define	PWR_PDCRC_PC14 PWR_PDCRC_PC14_Msk

#define	PWR_PDCRC_PC15_Pos (15U)

#define	PWR_PDCRC_PC15_Msk (0x1UL << PWR_PDCRC_PC15_Pos)

#define	PWR_PDCRC_PC15 PWR_PDCRC_PC15_Msk

#define	PWR_PUCRH_PH3_Pos (3U)

#define	PWR_PUCRH_PH3_Msk (0x1UL << PWR_PUCRH_PH3_Pos)

#define	PWR_PUCRH_PH3 PWR_PUCRH_PH3_Msk

#define	PWR_PDCRH_PH3_Pos (3U)

#define	PWR_PDCRH_PH3_Msk (0x1UL << PWR_PDCRH_PH3_Pos)

#define	PWR_PDCRH_PH3 PWR_PDCRH_PH3_Msk

#define	PWR_C2CR1_LPMS_Pos (0U)

#define	PWR_C2CR1_LPMS_Msk (0x7UL << PWR_C2CR1_LPMS_Pos)

#define	PWR_C2CR1_LPMS PWR_C2CR1_LPMS_Msk

#define	PWR_C2CR1_LPMS_0 (0x1UL << PWR_C2CR1_LPMS_Pos)

#define	PWR_C2CR1_LPMS_1 (0x2UL << PWR_C2CR1_LPMS_Pos)

#define	PWR_C2CR1_LPMS_2 (0x4UL << PWR_C2CR1_LPMS_Pos)

#define	PWR_C2CR1_FPDR_Pos (4U)

#define	PWR_C2CR1_FPDR_Msk (0x1UL << PWR_C2CR1_FPDR_Pos)

#define	PWR_C2CR1_FPDR PWR_C2CR1_FPDR_Msk

#define	PWR_C2CR1_FPDS_Pos (5U)

#define	PWR_C2CR1_FPDS_Msk (0x1UL << PWR_C2CR1_FPDS_Pos)

#define	PWR_C2CR1_FPDS PWR_C2CR1_FPDS_Msk

#define	PWR_C2CR3_EWUP_Pos (0U)

#define	PWR_C2CR3_EWUP_Msk (0x07UL << PWR_C2CR3_EWUP_Pos)

#define	PWR_C2CR3_EWUP PWR_C2CR3_EWUP_Msk

#define	PWR_C2CR3_EWUP1_Pos (0U)

#define	PWR_C2CR3_EWUP1_Msk (0x1UL << PWR_C2CR3_EWUP1_Pos)

#define	PWR_C2CR3_EWUP1 PWR_C2CR3_EWUP1_Msk

#define	PWR_C2CR3_EWUP2_Pos (1U)

#define	PWR_C2CR3_EWUP2_Msk (0x1UL << PWR_C2CR3_EWUP2_Pos)

#define	PWR_C2CR3_EWUP2 PWR_C2CR3_EWUP2_Msk

#define	PWR_C2CR3_EWUP3_Pos (2U)

#define	PWR_C2CR3_EWUP3_Msk (0x1UL << PWR_C2CR3_EWUP3_Pos)

#define	PWR_C2CR3_EWUP3 PWR_C2CR3_EWUP3_Msk

#define	PWR_C2CR3_EWPVD_Pos (8U)

#define	PWR_C2CR3_EWPVD_Msk (0x1UL << PWR_C2CR3_EWPVD_Pos)

#define	PWR_C2CR3_EWPVD PWR_C2CR3_EWPVD_Msk

#define	PWR_C2CR3_APC_Pos (10U)

#define	PWR_C2CR3_APC_Msk (0x1UL << PWR_C2CR3_APC_Pos)

#define	PWR_C2CR3_APC PWR_C2CR3_APC_Msk

#define	PWR_C2CR3_EWRFBUSY_Pos (11U)

#define	PWR_C2CR3_EWRFBUSY_Msk (0x1UL << PWR_C2CR3_EWRFBUSY_Pos)

#define	PWR_C2CR3_EWRFBUSY PWR_C2CR3_EWRFBUSY_Msk

#define	PWR_C2CR3_EWRFIRQ_Pos (13U)

#define	PWR_C2CR3_EWRFIRQ_Msk (0x1UL << PWR_C2CR3_EWRFIRQ_Pos)

#define	PWR_C2CR3_EWRFIRQ PWR_C2CR3_EWRFIRQ_Msk

#define	PWR_C2CR3_EIWUL_Pos (15U)

#define	PWR_C2CR3_EIWUL_Msk (0x1UL << PWR_C2CR3_EIWUL_Pos)

#define	PWR_C2CR3_EIWUL PWR_C2CR3_EIWUL_Msk

#define	PWR_EXTSCR_C1CSSF_Pos (0U)

#define	PWR_EXTSCR_C1CSSF_Msk (0x1UL << PWR_EXTSCR_C1CSSF_Pos)

#define	PWR_EXTSCR_C1CSSF PWR_EXTSCR_C1CSSF_Msk

#define	PWR_EXTSCR_C2CSSF_Pos (1U)

#define	PWR_EXTSCR_C2CSSF_Msk (0x1UL << PWR_EXTSCR_C2CSSF_Pos)

#define	PWR_EXTSCR_C2CSSF PWR_EXTSCR_C2CSSF_Msk

#define	PWR_EXTSCR_C1SBF_Pos (8U)

#define	PWR_EXTSCR_C1SBF_Msk (0x1UL << PWR_EXTSCR_C1SBF_Pos)

#define	PWR_EXTSCR_C1SBF PWR_EXTSCR_C1SBF_Msk

#define	PWR_EXTSCR_C1STOP2F_Pos (9U)

#define	PWR_EXTSCR_C1STOP2F_Msk (0x1UL << PWR_EXTSCR_C1STOP2F_Pos)

#define	PWR_EXTSCR_C1STOP2F PWR_EXTSCR_C1STOP2F_Msk

#define	PWR_EXTSCR_C1STOPF_Pos (10U)

#define	PWR_EXTSCR_C1STOPF_Msk (0x1UL << PWR_EXTSCR_C1STOPF_Pos)

#define	PWR_EXTSCR_C1STOPF PWR_EXTSCR_C1STOPF_Msk

#define	PWR_EXTSCR_C2SBF_Pos (11U)

#define	PWR_EXTSCR_C2SBF_Msk (0x1UL << PWR_EXTSCR_C2SBF_Pos)

#define	PWR_EXTSCR_C2SBF PWR_EXTSCR_C2SBF_Msk

#define	PWR_EXTSCR_C2STOP2F_Pos (12U)

#define	PWR_EXTSCR_C2STOP2F_Msk (0x1UL << PWR_EXTSCR_C2STOP2F_Pos)

#define	PWR_EXTSCR_C2STOP2F PWR_EXTSCR_C2STOP2F_Msk

#define	PWR_EXTSCR_C2STOPF_Pos (13U)

#define	PWR_EXTSCR_C2STOPF_Msk (0x1UL << PWR_EXTSCR_C2STOPF_Pos)

#define	PWR_EXTSCR_C2STOPF PWR_EXTSCR_C2STOPF_Msk

#define	PWR_EXTSCR_C1DS_Pos (14U)

#define	PWR_EXTSCR_C1DS_Msk (0x1UL << PWR_EXTSCR_C1DS_Pos)

#define	PWR_EXTSCR_C1DS PWR_EXTSCR_C1DS_Msk

#define	PWR_EXTSCR_C2DS_Pos (15U)

#define	PWR_EXTSCR_C2DS_Msk (0x1UL << PWR_EXTSCR_C2DS_Pos)

#define	PWR_EXTSCR_C2DS PWR_EXTSCR_C2DS_Msk

#define	PWR_SECCFGR_C2EWILA_Pos (15U)

#define	PWR_SECCFGR_C2EWILA_Msk (0x1UL << PWR_SECCFGR_C2EWILA_Pos)

#define	PWR_SECCFGR_C2EWILA PWR_SECCFGR_C2EWILA_Msk

#define	PWR_SUBGHZSPICR_NSS_Pos (15U)

#define	PWR_SUBGHZSPICR_NSS_Msk (0x1UL << PWR_SUBGHZSPICR_NSS_Pos)

#define	PWR_SUBGHZSPICR_NSS PWR_SUBGHZSPICR_NSS_Msk

#define	PWR_RSSCMDR_RSSCMD_Pos (0U)

#define	PWR_RSSCMDR_RSSCMD_Msk (0xFFUL << PWR_RSSCMDR_RSSCMD_Pos)

#define	PWR_RSSCMDR_RSSCMD PWR_RSSCMDR_RSSCMD_Msk

#define	PWR_RSSCMDR_RSSCMD_0 (0x01UL << PWR_RSSCMDR_RSSCMD_Pos)

#define	PWR_RSSCMDR_RSSCMD_1 (0x02UL << PWR_RSSCMDR_RSSCMD_Pos)

#define	PWR_RSSCMDR_RSSCMD_2 (0x04UL << PWR_RSSCMDR_RSSCMD_Pos)

#define	PWR_RSSCMDR_RSSCMD_3 (0x08UL << PWR_RSSCMDR_RSSCMD_Pos)

#define	PWR_RSSCMDR_RSSCMD_4 (0x10UL << PWR_RSSCMDR_RSSCMD_Pos)

#define	PWR_RSSCMDR_RSSCMD_5 (0x20UL << PWR_RSSCMDR_RSSCMD_Pos)

#define	PWR_RSSCMDR_RSSCMD_6 (0x40UL << PWR_RSSCMDR_RSSCMD_Pos)

#define	PWR_RSSCMDR_RSSCMD_7 (0x80UL << PWR_RSSCMDR_RSSCMD_Pos)

#define	RCC_CR_MSION_Pos (0U)

#define	RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos)

#define	RCC_CR_MSION RCC_CR_MSION_Msk

#define	RCC_CR_MSIRDY_Pos (1U)

#define	RCC_CR_MSIRDY_Msk (0x1UL << RCC_CR_MSIRDY_Pos)

#define	RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk

#define	RCC_CR_MSIPLLEN_Pos (2U)

#define	RCC_CR_MSIPLLEN_Msk (0x1UL << RCC_CR_MSIPLLEN_Pos)

#define	RCC_CR_MSIPLLEN RCC_CR_MSIPLLEN_Msk

#define	RCC_CR_MSIRGSEL_Pos (3U)

#define	RCC_CR_MSIRGSEL_Msk (0x1UL << RCC_CR_MSIRGSEL_Pos)

#define	RCC_CR_MSIRGSEL RCC_CR_MSIRGSEL_Msk

#define	RCC_CR_MSIRANGE_Pos (4U)

#define	RCC_CR_MSIRANGE_Msk (0xFUL << RCC_CR_MSIRANGE_Pos)

#define	RCC_CR_MSIRANGE RCC_CR_MSIRANGE_Msk

#define	RCC_CR_MSIRANGE_0 (0x0UL << RCC_CR_MSIRANGE_Pos)

#define	RCC_CR_MSIRANGE_1 (0x1UL << RCC_CR_MSIRANGE_Pos)

#define	RCC_CR_MSIRANGE_2 (0x2UL << RCC_CR_MSIRANGE_Pos)

#define	RCC_CR_MSIRANGE_3 (0x3UL << RCC_CR_MSIRANGE_Pos)

#define	RCC_CR_MSIRANGE_4 (0x4UL << RCC_CR_MSIRANGE_Pos)

#define	RCC_CR_MSIRANGE_5 (0x5UL << RCC_CR_MSIRANGE_Pos)

#define	RCC_CR_MSIRANGE_6 (0x6UL << RCC_CR_MSIRANGE_Pos)

#define	RCC_CR_MSIRANGE_7 (0x7UL << RCC_CR_MSIRANGE_Pos)

#define	RCC_CR_MSIRANGE_8 (0x8UL << RCC_CR_MSIRANGE_Pos)

#define	RCC_CR_MSIRANGE_9 (0x9UL << RCC_CR_MSIRANGE_Pos)

#define	RCC_CR_MSIRANGE_10 (0xAUL << RCC_CR_MSIRANGE_Pos)

#define	RCC_CR_MSIRANGE_11 (0xBUL << RCC_CR_MSIRANGE_Pos)

#define	RCC_CR_HSION_Pos (8U)

#define	RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)

#define	RCC_CR_HSION RCC_CR_HSION_Msk

#define	RCC_CR_HSIKERON_Pos (9U)

#define	RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos)

#define	RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk

#define	RCC_CR_HSIRDY_Pos (10U)

#define	RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)

#define	RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk

#define	RCC_CR_HSIASFS_Pos (11U)

#define	RCC_CR_HSIASFS_Msk (0x1UL << RCC_CR_HSIASFS_Pos)

#define	RCC_CR_HSIASFS RCC_CR_HSIASFS_Msk

#define	RCC_CR_HSIKERDY_Pos (12U)

#define	RCC_CR_HSIKERDY_Msk (0x1UL << RCC_CR_HSIKERDY_Pos)

#define	RCC_CR_HSIKERDY RCC_CR_HSIKERDY_Msk

#define	RCC_CR_HSEON_Pos (16U)

#define	RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)

#define	RCC_CR_HSEON RCC_CR_HSEON_Msk

#define	RCC_CR_HSERDY_Pos (17U)

#define	RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)

#define	RCC_CR_HSERDY RCC_CR_HSERDY_Msk

#define	RCC_CR_CSSON_Pos (19U)

#define	RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos)

#define	RCC_CR_CSSON RCC_CR_CSSON_Msk

#define	RCC_CR_HSEPRE_Pos (20U)

#define	RCC_CR_HSEPRE_Msk (0x1UL << RCC_CR_HSEPRE_Pos)

#define	RCC_CR_HSEPRE RCC_CR_HSEPRE_Msk

#define	RCC_CR_HSEBYPPWR_Pos (21U)

#define	RCC_CR_HSEBYPPWR_Msk (0x1UL << RCC_CR_HSEBYPPWR_Pos)

#define	RCC_CR_HSEBYPPWR RCC_CR_HSEBYPPWR_Msk

#define	RCC_CR_PLLON_Pos (24U)

#define	RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)

#define	RCC_CR_PLLON RCC_CR_PLLON_Msk

#define	RCC_CR_PLLRDY_Pos (25U)

#define	RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)

#define	RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk

#define	RCC_ICSCR_MSICAL_Pos (0U)

#define	RCC_ICSCR_MSICAL_Msk (0xFFUL << RCC_ICSCR_MSICAL_Pos)

#define	RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk

#define	RCC_ICSCR_MSITRIM_Pos (8U)

#define	RCC_ICSCR_MSITRIM_Msk (0xFFUL << RCC_ICSCR_MSITRIM_Pos)

#define	RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk

#define	RCC_ICSCR_HSICAL_Pos (16U)

#define	RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos)

#define	RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk

#define	RCC_ICSCR_HSITRIM_Pos (24U)

#define	RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos)

#define	RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk

#define	RCC_CFGR_SW_Pos (0U)

#define	RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)

#define	RCC_CFGR_SW RCC_CFGR_SW_Msk

#define	RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)

#define	RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)

#define	RCC_CFGR_SWS_Pos (2U)

#define	RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)

#define	RCC_CFGR_SWS RCC_CFGR_SWS_Msk

#define	RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)

#define	RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)

#define	RCC_CFGR_HPRE_Pos (4U)

#define	RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)

#define	RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk

#define	RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)

#define	RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)

#define	RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)

#define	RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)

#define	RCC_CFGR_PPRE1_Pos (8U)

#define	RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos)

#define	RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk

#define	RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos)

#define	RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos)

#define	RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos)

#define	RCC_CFGR_PPRE2_Pos (11U)

#define	RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos)

#define	RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk

#define	RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos)

#define	RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos)

#define	RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos)

#define	RCC_CFGR_STOPWUCK_Pos (15U)

#define	RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos)

#define	RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk

#define	RCC_CFGR_HPREF_Pos (16U)

#define	RCC_CFGR_HPREF_Msk (0x1UL << RCC_CFGR_HPREF_Pos)

#define	RCC_CFGR_HPREF RCC_CFGR_HPREF_Msk

#define	RCC_CFGR_PPRE1F_Pos (17U)

#define	RCC_CFGR_PPRE1F_Msk (0x1UL << RCC_CFGR_PPRE1F_Pos)

#define	RCC_CFGR_PPRE1F RCC_CFGR_PPRE1F_Msk

#define	RCC_CFGR_PPRE2F_Pos (18U)

#define	RCC_CFGR_PPRE2F_Msk (0x1UL << RCC_CFGR_PPRE2F_Pos)

#define	RCC_CFGR_PPRE2F RCC_CFGR_PPRE2F_Msk

#define	RCC_CFGR_MCOSEL_Pos (24U)

#define	RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos)

#define	RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk

#define	RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos)

#define	RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos)

#define	RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos)

#define	RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos)

#define	RCC_CFGR_MCOPRE_Pos (28U)

#define	RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos)

#define	RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk

#define	RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos)

#define	RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos)

#define	RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos)

#define	RCC_PLLCFGR_PLLSRC_Pos (0U)

#define	RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos

#define	RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk

#define	RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos

#define	RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos

#define	RCC_PLLCFGR_PLLM_Pos (4U)

#define	RCC_PLLCFGR_PLLM_Msk (0x7UL << RCC_PLLCFGR_PLLM_Pos)

#define	RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk

#define	RCC_PLLCFGR_PLLM_0 (0x1UL << RCC_PLLCFGR_PLLM_Pos)

#define	RCC_PLLCFGR_PLLM_1 (0x2UL << RCC_PLLCFGR_PLLM_Pos)

#define	RCC_PLLCFGR_PLLM_2 (0x4UL << RCC_PLLCFGR_PLLM_Pos)

#define	RCC_PLLCFGR_PLLN_Pos (8U)

#define	RCC_PLLCFGR_PLLN_Msk (0x7FUL << RCC_PLLCFGR_PLLN_Pos

#define	RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk

#define	RCC_PLLCFGR_PLLN_0 (0x01UL << RCC_PLLCFGR_PLLN_Pos

#define	RCC_PLLCFGR_PLLN_1 (0x02UL << RCC_PLLCFGR_PLLN_Pos

#define	RCC_PLLCFGR_PLLN_2 (0x04UL << RCC_PLLCFGR_PLLN_Pos

#define	RCC_PLLCFGR_PLLN_3 (0x08UL << RCC_PLLCFGR_PLLN_Pos

#define	RCC_PLLCFGR_PLLN_4 (0x10UL << RCC_PLLCFGR_PLLN_Pos

#define	RCC_PLLCFGR_PLLN_5 (0x20UL << RCC_PLLCFGR_PLLN_Pos

#define	RCC_PLLCFGR_PLLN_6 (0x40UL << RCC_PLLCFGR_PLLN_Pos

#define	RCC_PLLCFGR_PLLPEN_Pos (16U)

#define	RCC_PLLCFGR_PLLPEN_Msk (0x1UL << RCC_PLLCFGR_PLLPEN_Pos

#define	RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk

#define	RCC_PLLCFGR_PLLP_Pos (17U)

#define	RCC_PLLCFGR_PLLP_Msk (0x1FUL << RCC_PLLCFGR_PLLP_Pos

#define	RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk

#define	RCC_PLLCFGR_PLLP_0 (0x01UL << RCC_PLLCFGR_PLLP_Pos

#define	RCC_PLLCFGR_PLLP_1 (0x02UL << RCC_PLLCFGR_PLLP_Pos

#define	RCC_PLLCFGR_PLLP_2 (0x04UL << RCC_PLLCFGR_PLLP_Pos

#define	RCC_PLLCFGR_PLLP_3 (0x08UL << RCC_PLLCFGR_PLLP_Pos

#define	RCC_PLLCFGR_PLLP_4 (0x10UL << RCC_PLLCFGR_PLLP_Pos

#define	RCC_PLLCFGR_PLLQEN_Pos (24U)

#define	RCC_PLLCFGR_PLLQEN_Msk (0x1UL << RCC_PLLCFGR_PLLQEN_Pos

#define	RCC_PLLCFGR_PLLQEN RCC_PLLCFGR_PLLQEN_Msk

#define	RCC_PLLCFGR_PLLQ_Pos (25U)

#define	RCC_PLLCFGR_PLLQ_Msk (0x7UL << RCC_PLLCFGR_PLLQ_Pos

#define	RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk

#define	RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos

#define	RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos

#define	RCC_PLLCFGR_PLLQ_2 (0x4UL << RCC_PLLCFGR_PLLQ_Pos

#define	RCC_PLLCFGR_PLLREN_Pos (28U)

#define	RCC_PLLCFGR_PLLREN_Msk (0x1UL << RCC_PLLCFGR_PLLREN_Pos

#define	RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk

#define	RCC_PLLCFGR_PLLR_Pos (29U)

#define	RCC_PLLCFGR_PLLR_Msk (0x7UL << RCC_PLLCFGR_PLLR_Pos

#define	RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk

#define	RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos

#define	RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos

#define	RCC_PLLCFGR_PLLR_2 (0x4UL << RCC_PLLCFGR_PLLR_Pos

#define	RCC_CIER_LSIRDYIE_Pos (0U)

#define	RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos)

#define	RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk

#define	RCC_CIER_LSERDYIE_Pos (1U)

#define	RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos)

#define	RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk

#define	RCC_CIER_MSIRDYIE_Pos (2U)

#define	RCC_CIER_MSIRDYIE_Msk (0x1UL << RCC_CIER_MSIRDYIE_Pos)

#define	RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk

#define	RCC_CIER_HSIRDYIE_Pos (3U)

#define	RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos)

#define	RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk

#define	RCC_CIER_HSERDYIE_Pos (4U)

#define	RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos)

#define	RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk

#define	RCC_CIER_PLLRDYIE_Pos (5U)

#define	RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos

#define	RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk

#define	RCC_CIER_LSECSSIE_Pos (9U)

#define	RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos)

#define	RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk

#define	RCC_CIFR_LSIRDYF_Pos (0U)

#define	RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos)

#define	RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk

#define	RCC_CIFR_LSERDYF_Pos (1U)

#define	RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos)

#define	RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk

#define	RCC_CIFR_MSIRDYF_Pos (2U)

#define	RCC_CIFR_MSIRDYF_Msk (0x1UL << RCC_CIFR_MSIRDYF_Pos)

#define	RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk

#define	RCC_CIFR_HSIRDYF_Pos (3U)

#define	RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos)

#define	RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk

#define	RCC_CIFR_HSERDYF_Pos (4U)

#define	RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos)

#define	RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk

#define	RCC_CIFR_PLLRDYF_Pos (5U)

#define	RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos

#define	RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk

#define	RCC_CIFR_CSSF_Pos (8U)

#define	RCC_CIFR_CSSF_Msk (0x1UL << RCC_CIFR_CSSF_Pos)

#define	RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk

#define	RCC_CIFR_LSECSSF_Pos (9U)

#define	RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos)

#define	RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk

#define	RCC_CICR_LSIRDYC_Pos (0U)

#define	RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos)

#define	RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk

#define	RCC_CICR_LSERDYC_Pos (1U)

#define	RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos)

#define	RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk

#define	RCC_CICR_MSIRDYC_Pos (2U)

#define	RCC_CICR_MSIRDYC_Msk (0x1UL << RCC_CICR_MSIRDYC_Pos)

#define	RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk

#define	RCC_CICR_HSIRDYC_Pos (3U)

#define	RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos)

#define	RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk

#define	RCC_CICR_HSERDYC_Pos (4U)

#define	RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos)

#define	RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk

#define	RCC_CICR_PLLRDYC_Pos (5U)

#define	RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos

#define	RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk

#define	RCC_CICR_CSSC_Pos (8U)

#define	RCC_CICR_CSSC_Msk (0x1UL << RCC_CICR_CSSC_Pos)

#define	RCC_CICR_CSSC RCC_CICR_CSSC_Msk

#define	RCC_CICR_LSECSSC_Pos (9U)

#define	RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos)

#define	RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk

#define	RCC_AHB1RSTR_DMA1RST_Pos (0U)

#define	RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos

#define	RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk

#define	RCC_AHB1RSTR_DMA2RST_Pos (1U)

#define	RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos

#define	RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk

#define	RCC_AHB1RSTR_DMAMUX1RST_Pos (2U)

#define	RCC_AHB1RSTR_DMAMUX1RST_Msk (0x1UL << RCC_AHB1RSTR_DMAMUX1RST_Pos

#define	RCC_AHB1RSTR_DMAMUX1RST RCC_AHB1RSTR_DMAMUX1RST_Msk

#define	RCC_AHB1RSTR_CRCRST_Pos (12U)

#define	RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos

#define	RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk

#define	RCC_AHB2RSTR_GPIOARST_Pos (0U)

#define	RCC_AHB2RSTR_GPIOARST_Msk (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos

#define	RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk

#define	RCC_AHB2RSTR_GPIOBRST_Pos (1U)

#define	RCC_AHB2RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos

#define	RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk

#define	RCC_AHB2RSTR_GPIOCRST_Pos (2U)

#define	RCC_AHB2RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos

#define	RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk

#define	RCC_AHB2RSTR_GPIOHRST_Pos (7U)

#define	RCC_AHB2RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOHRST_Pos

#define	RCC_AHB2RSTR_GPIOHRST RCC_AHB2RSTR_GPIOHRST_Msk

#define	RCC_AHB3RSTR_PKARST_Pos (16U)

#define	RCC_AHB3RSTR_PKARST_Msk (0x1UL << RCC_AHB3RSTR_PKARST_Pos)

#define	RCC_AHB3RSTR_PKARST RCC_AHB3RSTR_PKARST_Msk

#define	RCC_AHB3RSTR_AESRST_Pos (17U)

#define	RCC_AHB3RSTR_AESRST_Msk (0x1UL << RCC_AHB3RSTR_AESRST_Pos

#define	RCC_AHB3RSTR_AESRST RCC_AHB3RSTR_AESRST_Msk

#define	RCC_AHB3RSTR_RNGRST_Pos (18U)

#define	RCC_AHB3RSTR_RNGRST_Msk (0x1UL << RCC_AHB3RSTR_RNGRST_Pos

#define	RCC_AHB3RSTR_RNGRST RCC_AHB3RSTR_RNGRST_Msk

#define	RCC_AHB3RSTR_HSEMRST_Pos (19U)

#define	RCC_AHB3RSTR_HSEMRST_Msk (0x1UL << RCC_AHB3RSTR_HSEMRST_Pos

#define	RCC_AHB3RSTR_HSEMRST RCC_AHB3RSTR_HSEMRST_Msk

#define	RCC_AHB3RSTR_IPCCRST_Pos (20U)

#define	RCC_AHB3RSTR_IPCCRST_Msk (0x1UL << RCC_AHB3RSTR_IPCCRST_Pos

#define	RCC_AHB3RSTR_IPCCRST RCC_AHB3RSTR_IPCCRST_Msk

#define	RCC_AHB3RSTR_FLASHRST_Pos (25U)

#define	RCC_AHB3RSTR_FLASHRST_Msk (0x1UL << RCC_AHB3RSTR_FLASHRST_Pos)

#define	RCC_AHB3RSTR_FLASHRST RCC_AHB3RSTR_FLASHRST_Msk

#define	RCC_APB1RSTR1_TIM2RST_Pos (0U)

#define	RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos

#define	RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk

#define	RCC_APB1RSTR1_SPI2RST_Pos (14U)

#define	RCC_APB1RSTR1_SPI2RST_Msk (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos

#define	RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk

#define	RCC_APB1RSTR1_USART2RST_Pos (17U)

#define	RCC_APB1RSTR1_USART2RST_Msk (0x1UL << RCC_APB1RSTR1_USART2RST_Pos

#define	RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk

#define	RCC_APB1RSTR1_I2C1RST_Pos (21U)

#define	RCC_APB1RSTR1_I2C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos

#define	RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk

#define	RCC_APB1RSTR1_I2C2RST_Pos (22U)

#define	RCC_APB1RSTR1_I2C2RST_Msk (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos

#define	RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk

#define	RCC_APB1RSTR1_I2C3RST_Pos (23U)

#define	RCC_APB1RSTR1_I2C3RST_Msk (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos

#define	RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk

#define	RCC_APB1RSTR1_DACRST_Pos (29U)

#define	RCC_APB1RSTR1_DACRST_Msk (0x1UL << RCC_APB1RSTR1_DACRST_Pos

#define	RCC_APB1RSTR1_DACRST RCC_APB1RSTR1_DACRST_Msk

#define	RCC_APB1RSTR1_LPTIM1RST_Pos (31U)

#define	RCC_APB1RSTR1_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos

#define	RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk

#define	RCC_APB1RSTR2_LPUART1RST_Pos (0U)

#define	RCC_APB1RSTR2_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR2_LPUART1RST_Pos

#define	RCC_APB1RSTR2_LPUART1RST RCC_APB1RSTR2_LPUART1RST_Msk

#define	RCC_APB1RSTR2_LPTIM2RST_Pos (5U)

#define	RCC_APB1RSTR2_LPTIM2RST_Msk (0x1UL << RCC_APB1RSTR2_LPTIM2RST_Pos

#define	RCC_APB1RSTR2_LPTIM2RST RCC_APB1RSTR2_LPTIM2RST_Msk

#define	RCC_APB1RSTR2_LPTIM3RST_Pos (6U)

#define	RCC_APB1RSTR2_LPTIM3RST_Msk (0x1UL << RCC_APB1RSTR2_LPTIM3RST_Pos

#define	RCC_APB1RSTR2_LPTIM3RST RCC_APB1RSTR2_LPTIM3RST_Msk

#define	RCC_APB2RSTR_ADCRST_Pos (9U)

#define	RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos

#define	RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk

#define	RCC_APB2RSTR_TIM1RST_Pos (11U)

#define	RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos

#define	RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk

#define	RCC_APB2RSTR_SPI1RST_Pos (12U)

#define	RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos

#define	RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk

#define	RCC_APB2RSTR_USART1RST_Pos (14U)

#define	RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos

#define	RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk

#define	RCC_APB2RSTR_TIM16RST_Pos (17U)

#define	RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos

#define	RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk

#define	RCC_APB2RSTR_TIM17RST_Pos (18U)

#define	RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos

#define	RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk

#define	RCC_APB3RSTR_SUBGHZSPIRST_Pos (0U)

#define	RCC_APB3RSTR_SUBGHZSPIRST_Msk (0x1UL << RCC_APB3RSTR_SUBGHZSPIRST_Pos)

#define	RCC_APB3RSTR_SUBGHZSPIRST RCC_APB3RSTR_SUBGHZSPIRST_Msk

#define	RCC_AHB1ENR_DMA1EN_Pos (0U)

#define	RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)

#define	RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk

#define	RCC_AHB1ENR_DMA2EN_Pos (1U)

#define	RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)

#define	RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk

#define	RCC_AHB1ENR_DMAMUX1EN_Pos (2U)

#define	RCC_AHB1ENR_DMAMUX1EN_Msk (0x1UL << RCC_AHB1ENR_DMAMUX1EN_Pos

#define	RCC_AHB1ENR_DMAMUX1EN RCC_AHB1ENR_DMAMUX1EN_Msk

#define	RCC_AHB1ENR_CRCEN_Pos (12U)

#define	RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos)

#define	RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk

#define	RCC_AHB2ENR_GPIOAEN_Pos (0U)

#define	RCC_AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos)

#define	RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk

#define	RCC_AHB2ENR_GPIOBEN_Pos (1U)

#define	RCC_AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos)

#define	RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk

#define	RCC_AHB2ENR_GPIOCEN_Pos (2U)

#define	RCC_AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos)

#define	RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk

#define	RCC_AHB2ENR_GPIOHEN_Pos (7U)

#define	RCC_AHB2ENR_GPIOHEN_Msk (0x1UL << RCC_AHB2ENR_GPIOHEN_Pos)

#define	RCC_AHB2ENR_GPIOHEN RCC_AHB2ENR_GPIOHEN_Msk

#define	RCC_AHB3ENR_PKAEN_Pos (16U)

#define	RCC_AHB3ENR_PKAEN_Msk (0x1UL << RCC_AHB3ENR_PKAEN_Pos)

#define	RCC_AHB3ENR_PKAEN RCC_AHB3ENR_PKAEN_Msk

#define	RCC_AHB3ENR_AESEN_Pos (17U)

#define	RCC_AHB3ENR_AESEN_Msk (0x1UL << RCC_AHB3ENR_AESEN_Pos

#define	RCC_AHB3ENR_AESEN RCC_AHB3ENR_AESEN_Msk

#define	RCC_AHB3ENR_RNGEN_Pos (18U)

#define	RCC_AHB3ENR_RNGEN_Msk (0x1UL << RCC_AHB3ENR_RNGEN_Pos)

#define	RCC_AHB3ENR_RNGEN RCC_AHB3ENR_RNGEN_Msk

#define	RCC_AHB3ENR_HSEMEN_Pos (19U)

#define	RCC_AHB3ENR_HSEMEN_Msk (0x1UL << RCC_AHB3ENR_HSEMEN_Pos)

#define	RCC_AHB3ENR_HSEMEN RCC_AHB3ENR_HSEMEN_Msk

#define	RCC_AHB3ENR_IPCCEN_Pos (20U)

#define	RCC_AHB3ENR_IPCCEN_Msk (0x1UL << RCC_AHB3ENR_IPCCEN_Pos)

#define	RCC_AHB3ENR_IPCCEN RCC_AHB3ENR_IPCCEN_Msk

#define	RCC_AHB3ENR_FLASHEN_Pos (25U)

#define	RCC_AHB3ENR_FLASHEN_Msk (0x1UL << RCC_AHB3ENR_FLASHEN_Pos)

#define	RCC_AHB3ENR_FLASHEN RCC_AHB3ENR_FLASHEN_Msk

#define	RCC_APB1ENR1_TIM2EN_Pos (0U)

#define	RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos)

#define	RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk

#define	RCC_APB1ENR1_RTCAPBEN_Pos (10U)

#define	RCC_APB1ENR1_RTCAPBEN_Msk (0x1UL << RCC_APB1ENR1_RTCAPBEN_Pos

#define	RCC_APB1ENR1_RTCAPBEN RCC_APB1ENR1_RTCAPBEN_Msk

#define	RCC_APB1ENR1_WWDGEN_Pos (11U)

#define	RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos)

#define	RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk

#define	RCC_APB1ENR1_SPI2EN_Pos (14U)

#define	RCC_APB1ENR1_SPI2EN_Msk (0x1UL << RCC_APB1ENR1_SPI2EN_Pos)

#define	RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk

#define	RCC_APB1ENR1_USART2EN_Pos (17U)

#define	RCC_APB1ENR1_USART2EN_Msk (0x1UL << RCC_APB1ENR1_USART2EN_Pos)

#define	RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk

#define	RCC_APB1ENR1_I2C1EN_Pos (21U)

#define	RCC_APB1ENR1_I2C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1EN_Pos)

#define	RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk

#define	RCC_APB1ENR1_I2C2EN_Pos (22U)

#define	RCC_APB1ENR1_I2C2EN_Msk (0x1UL << RCC_APB1ENR1_I2C2EN_Pos)

#define	RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk

#define	RCC_APB1ENR1_I2C3EN_Pos (23U)

#define	RCC_APB1ENR1_I2C3EN_Msk (0x1UL << RCC_APB1ENR1_I2C3EN_Pos)

#define	RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk

#define	RCC_APB1ENR1_DACEN_Pos (29U)

#define	RCC_APB1ENR1_DACEN_Msk (0x1UL << RCC_APB1ENR1_DACEN_Pos

#define	RCC_APB1ENR1_DACEN RCC_APB1ENR1_DACEN_Msk

#define	RCC_APB1ENR1_LPTIM1EN_Pos (31U)

#define	RCC_APB1ENR1_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos

#define	RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk

#define	RCC_APB1ENR2_LPUART1EN_Pos (0U)

#define	RCC_APB1ENR2_LPUART1EN_Msk (0x1UL << RCC_APB1ENR2_LPUART1EN_Pos

#define	RCC_APB1ENR2_LPUART1EN RCC_APB1ENR2_LPUART1EN_Msk

#define	RCC_APB1ENR2_LPTIM2EN_Pos (5U)

#define	RCC_APB1ENR2_LPTIM2EN_Msk (0x1UL << RCC_APB1ENR2_LPTIM2EN_Pos

#define	RCC_APB1ENR2_LPTIM2EN RCC_APB1ENR2_LPTIM2EN_Msk

#define	RCC_APB1ENR2_LPTIM3EN_Pos (6U)

#define	RCC_APB1ENR2_LPTIM3EN_Msk (0x1UL << RCC_APB1ENR2_LPTIM3EN_Pos

#define	RCC_APB1ENR2_LPTIM3EN RCC_APB1ENR2_LPTIM3EN_Msk

#define	RCC_APB2ENR_ADCEN_Pos (9U)

#define	RCC_APB2ENR_ADCEN_Msk (0x1UL << RCC_APB2ENR_ADCEN_Pos)

#define	RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk

#define	RCC_APB2ENR_TIM1EN_Pos (11U)

#define	RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)

#define	RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk

#define	RCC_APB2ENR_SPI1EN_Pos (12U)

#define	RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)

#define	RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk

#define	RCC_APB2ENR_USART1EN_Pos (14U)

#define	RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos

#define	RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk

#define	RCC_APB2ENR_TIM16EN_Pos (17U)

#define	RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos)

#define	RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk

#define	RCC_APB2ENR_TIM17EN_Pos (18U)

#define	RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos)

#define	RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk

#define	RCC_APB3ENR_SUBGHZSPIEN_Pos (0U)

#define	RCC_APB3ENR_SUBGHZSPIEN_Msk (0x1UL << RCC_APB3ENR_SUBGHZSPIEN_Pos

#define	RCC_APB3ENR_SUBGHZSPIEN RCC_APB3ENR_SUBGHZSPIEN_Msk

#define	RCC_AHB1SMENR_DMA1SMEN_Pos (0U)

#define	RCC_AHB1SMENR_DMA1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA1SMEN_Pos

#define	RCC_AHB1SMENR_DMA1SMEN RCC_AHB1SMENR_DMA1SMEN_Msk

#define	RCC_AHB1SMENR_DMA2SMEN_Pos (1U)

#define	RCC_AHB1SMENR_DMA2SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA2SMEN_Pos

#define	RCC_AHB1SMENR_DMA2SMEN RCC_AHB1SMENR_DMA2SMEN_Msk

#define	RCC_AHB1SMENR_DMAMUX1SMEN_Pos (2U)

#define	RCC_AHB1SMENR_DMAMUX1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMAMUX1SMEN_Pos

#define	RCC_AHB1SMENR_DMAMUX1SMEN RCC_AHB1SMENR_DMAMUX1SMEN_Msk

#define	RCC_AHB1SMENR_CRCSMEN_Pos (12U)

#define	RCC_AHB1SMENR_CRCSMEN_Msk (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos

#define	RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk

#define	RCC_AHB2SMENR_GPIOASMEN_Pos (0U)

#define	RCC_AHB2SMENR_GPIOASMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos

#define	RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk

#define	RCC_AHB2SMENR_GPIOBSMEN_Pos (1U)

#define	RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos

#define	RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk

#define	RCC_AHB2SMENR_GPIOCSMEN_Pos (2U)

#define	RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos

#define	RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk

#define	RCC_AHB2SMENR_GPIOHSMEN_Pos (7U)

#define	RCC_AHB2SMENR_GPIOHSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOHSMEN_Pos

#define	RCC_AHB2SMENR_GPIOHSMEN RCC_AHB2SMENR_GPIOHSMEN_Msk

#define	RCC_AHB3SMENR_PKASMEN_Pos (16U)

#define	RCC_AHB3SMENR_PKASMEN_Msk (0x1UL << RCC_AHB3SMENR_PKASMEN_Pos)

#define	RCC_AHB3SMENR_PKASMEN RCC_AHB3SMENR_PKASMEN_Msk

#define	RCC_AHB3SMENR_AESSMEN_Pos (17U)

#define	RCC_AHB3SMENR_AESSMEN_Msk (0x1UL << RCC_AHB3SMENR_AESSMEN_Pos)

#define	RCC_AHB3SMENR_AESSMEN RCC_AHB3SMENR_AESSMEN_Msk

#define	RCC_AHB3SMENR_RNGSMEN_Pos (18U)

#define	RCC_AHB3SMENR_RNGSMEN_Msk (0x1UL << RCC_AHB3SMENR_RNGSMEN_Pos

#define	RCC_AHB3SMENR_RNGSMEN RCC_AHB3SMENR_RNGSMEN_Msk

#define	RCC_AHB3SMENR_SRAM1SMEN_Pos (23U)

#define	RCC_AHB3SMENR_SRAM1SMEN_Msk (0x1UL << RCC_AHB3SMENR_SRAM1SMEN_Pos

#define	RCC_AHB3SMENR_SRAM1SMEN RCC_AHB3SMENR_SRAM1SMEN_Msk

#define	RCC_AHB3SMENR_SRAM2SMEN_Pos (24U)

#define	RCC_AHB3SMENR_SRAM2SMEN_Msk (0x1UL << RCC_AHB3SMENR_SRAM2SMEN_Pos

#define	RCC_AHB3SMENR_SRAM2SMEN RCC_AHB3SMENR_SRAM2SMEN_Msk

#define	RCC_AHB3SMENR_FLASHSMEN_Pos (25U)

#define	RCC_AHB3SMENR_FLASHSMEN_Msk (0x1UL << RCC_AHB3SMENR_FLASHSMEN_Pos

#define	RCC_AHB3SMENR_FLASHSMEN RCC_AHB3SMENR_FLASHSMEN_Msk

#define	RCC_APB1SMENR1_TIM2SMEN_Pos (0U)

#define	RCC_APB1SMENR1_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos

#define	RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk

#define	RCC_APB1SMENR1_RTCAPBSMEN_Pos (10U)

#define	RCC_APB1SMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APB1SMENR1_RTCAPBSMEN_Pos

#define	RCC_APB1SMENR1_RTCAPBSMEN RCC_APB1SMENR1_RTCAPBSMEN_Msk

#define	RCC_APB1SMENR1_WWDGSMEN_Pos (11U)

#define	RCC_APB1SMENR1_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos

#define	RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk

#define	RCC_APB1SMENR1_SPI2SMEN_Pos (14U)

#define	RCC_APB1SMENR1_SPI2SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI2SMEN_Pos

#define	RCC_APB1SMENR1_SPI2SMEN RCC_APB1SMENR1_SPI2SMEN_Msk

#define	RCC_APB1SMENR1_USART2SMEN_Pos (17U)

#define	RCC_APB1SMENR1_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos

#define	RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk

#define	RCC_APB1SMENR1_I2C1SMEN_Pos (21U)

#define	RCC_APB1SMENR1_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos

#define	RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk

#define	RCC_APB1SMENR1_I2C2SMEN_Pos (22U)

#define	RCC_APB1SMENR1_I2C2SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C2SMEN_Pos

#define	RCC_APB1SMENR1_I2C2SMEN RCC_APB1SMENR1_I2C2SMEN_Msk

#define	RCC_APB1SMENR1_I2C3SMEN_Pos (23U)

#define	RCC_APB1SMENR1_I2C3SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C3SMEN_Pos

#define	RCC_APB1SMENR1_I2C3SMEN RCC_APB1SMENR1_I2C3SMEN_Msk

#define	RCC_APB1SMENR1_DACSMEN_Pos (29U)

#define	RCC_APB1SMENR1_DACSMEN_Msk (0x1UL << RCC_APB1SMENR1_DACSMEN_Pos

#define	RCC_APB1SMENR1_DACSMEN RCC_APB1SMENR1_DACSMEN_Msk

#define	RCC_APB1SMENR1_LPTIM1SMEN_Pos (31U)

#define	RCC_APB1SMENR1_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR1_LPTIM1SMEN_Pos

#define	RCC_APB1SMENR1_LPTIM1SMEN RCC_APB1SMENR1_LPTIM1SMEN_Msk

#define	RCC_APB1SMENR2_LPUART1SMEN_Pos (0U)

#define	RCC_APB1SMENR2_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPUART1SMEN_Pos

#define	RCC_APB1SMENR2_LPUART1SMEN RCC_APB1SMENR2_LPUART1SMEN_Msk

#define	RCC_APB1SMENR2_LPTIM2SMEN_Pos (5U)

#define	RCC_APB1SMENR2_LPTIM2SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPTIM2SMEN_Pos

#define	RCC_APB1SMENR2_LPTIM2SMEN RCC_APB1SMENR2_LPTIM2SMEN_Msk

#define	RCC_APB1SMENR2_LPTIM3SMEN_Pos (6U)

#define	RCC_APB1SMENR2_LPTIM3SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPTIM3SMEN_Pos

#define	RCC_APB1SMENR2_LPTIM3SMEN RCC_APB1SMENR2_LPTIM3SMEN_Msk

#define	RCC_APB2SMENR_ADCSMEN_Pos (9U)

#define	RCC_APB2SMENR_ADCSMEN_Msk (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos

#define	RCC_APB2SMENR_ADCSMEN RCC_APB2SMENR_ADCSMEN_Msk

#define	RCC_APB2SMENR_TIM1SMEN_Pos (11U)

#define	RCC_APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos

#define	RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk

#define	RCC_APB2SMENR_SPI1SMEN_Pos (12U)

#define	RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos

#define	RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk

#define	RCC_APB2SMENR_USART1SMEN_Pos (14U)

#define	RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos

#define	RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk

#define	RCC_APB2SMENR_TIM16SMEN_Pos (17U)

#define	RCC_APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos

#define	RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk

#define	RCC_APB2SMENR_TIM17SMEN_Pos (18U)

#define	RCC_APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos

#define	RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk

#define	RCC_APB3SMENR_SUBGHZSPISMEN_Pos (0U)

#define	RCC_APB3SMENR_SUBGHZSPISMEN_Msk (0x1UL << RCC_APB3SMENR_SUBGHZSPISMEN_Pos

#define	RCC_APB3SMENR_SUBGHZSPISMEN RCC_APB3SMENR_SUBGHZSPISMEN_Msk

#define	RCC_CCIPR_USART1SEL_Pos (0U)

#define	RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos)

#define	RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk

#define	RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos)

#define	RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos)

#define	RCC_CCIPR_USART2SEL_Pos (2U)

#define	RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos)

#define	RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk

#define	RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos)

#define	RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos)

#define	RCC_CCIPR_I2S2SEL_Pos (8U)

#define	RCC_CCIPR_I2S2SEL_Msk (0x3UL << RCC_CCIPR_I2S2SEL_Pos)

#define	RCC_CCIPR_I2S2SEL RCC_CCIPR_I2S2SEL_Msk

#define	RCC_CCIPR_I2S2SEL_0 (0x1UL << RCC_CCIPR_I2S2SEL_Pos)

#define	RCC_CCIPR_I2S2SEL_1 (0x2UL << RCC_CCIPR_I2S2SEL_Pos)

#define	RCC_CCIPR_LPUART1SEL_Pos (10U)

#define	RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)

#define	RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk

#define	RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)

#define	RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)

#define	RCC_CCIPR_I2C1SEL_Pos (12U)

#define	RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos)

#define	RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk

#define	RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos)

#define	RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos)

#define	RCC_CCIPR_I2C2SEL_Pos (14U)

#define	RCC_CCIPR_I2C2SEL_Msk (0x3UL << RCC_CCIPR_I2C2SEL_Pos)

#define	RCC_CCIPR_I2C2SEL RCC_CCIPR_I2C2SEL_Msk

#define	RCC_CCIPR_I2C2SEL_0 (0x1UL << RCC_CCIPR_I2C2SEL_Pos)

#define	RCC_CCIPR_I2C2SEL_1 (0x2UL << RCC_CCIPR_I2C2SEL_Pos)

#define	RCC_CCIPR_I2C3SEL_Pos (16U)

#define	RCC_CCIPR_I2C3SEL_Msk (0x3UL << RCC_CCIPR_I2C3SEL_Pos)

#define	RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk

#define	RCC_CCIPR_I2C3SEL_0 (0x1UL << RCC_CCIPR_I2C3SEL_Pos)

#define	RCC_CCIPR_I2C3SEL_1 (0x2UL << RCC_CCIPR_I2C3SEL_Pos)

#define	RCC_CCIPR_LPTIM1SEL_Pos (18U)

#define	RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)

#define	RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk

#define	RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)

#define	RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)

#define	RCC_CCIPR_LPTIM2SEL_Pos (20U)

#define	RCC_CCIPR_LPTIM2SEL_Msk (0x3UL << RCC_CCIPR_LPTIM2SEL_Pos)

#define	RCC_CCIPR_LPTIM2SEL RCC_CCIPR_LPTIM2SEL_Msk

#define	RCC_CCIPR_LPTIM2SEL_0 (0x1UL << RCC_CCIPR_LPTIM2SEL_Pos)

#define	RCC_CCIPR_LPTIM2SEL_1 (0x2UL << RCC_CCIPR_LPTIM2SEL_Pos)

#define	RCC_CCIPR_LPTIM3SEL_Pos (22U)

#define	RCC_CCIPR_LPTIM3SEL_Msk (0x3UL << RCC_CCIPR_LPTIM3SEL_Pos)

#define	RCC_CCIPR_LPTIM3SEL RCC_CCIPR_LPTIM3SEL_Msk

#define	RCC_CCIPR_LPTIM3SEL_0 (0x1UL << RCC_CCIPR_LPTIM3SEL_Pos)

#define	RCC_CCIPR_LPTIM3SEL_1 (0x2UL << RCC_CCIPR_LPTIM3SEL_Pos)

#define	RCC_CCIPR_ADCSEL_Pos (28U)

#define	RCC_CCIPR_ADCSEL_Msk (0x3UL << RCC_CCIPR_ADCSEL_Pos)

#define	RCC_CCIPR_ADCSEL RCC_CCIPR_ADCSEL_Msk

#define	RCC_CCIPR_ADCSEL_0 (0x1UL << RCC_CCIPR_ADCSEL_Pos)

#define	RCC_CCIPR_ADCSEL_1 (0x2UL << RCC_CCIPR_ADCSEL_Pos)

#define	RCC_CCIPR_RNGSEL_Pos (30U)

#define	RCC_CCIPR_RNGSEL_Msk (0x3UL << RCC_CCIPR_RNGSEL_Pos)

#define	RCC_CCIPR_RNGSEL RCC_CCIPR_RNGSEL_Msk

#define	RCC_CCIPR_RNGSEL_0 (0x1UL << RCC_CCIPR_RNGSEL_Pos)

#define	RCC_CCIPR_RNGSEL_1 (0x2UL << RCC_CCIPR_RNGSEL_Pos)

#define	RCC_BDCR_LSEON_Pos (0U)

#define	RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)

#define	RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk

#define	RCC_BDCR_LSERDY_Pos (1U)

#define	RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)

#define	RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk

#define	RCC_BDCR_LSEBYP_Pos (2U)

#define	RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)

#define	RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk

#define	RCC_BDCR_LSEDRV_Pos (3U)

#define	RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos)

#define	RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk

#define	RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos)

#define	RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos)

#define	RCC_BDCR_LSECSSON_Pos (5U)

#define	RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos)

#define	RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk

#define	RCC_BDCR_LSECSSD_Pos (6U)

#define	RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos)

#define	RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk

#define	RCC_BDCR_LSESYSEN_Pos (7U)

#define	RCC_BDCR_LSESYSEN_Msk (0x1UL << RCC_BDCR_LSESYSEN_Pos)

#define	RCC_BDCR_LSESYSEN RCC_BDCR_LSESYSEN_Msk

#define	RCC_BDCR_RTCSEL_Pos (8U)

#define	RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)

#define	RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk

#define	RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)

#define	RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)

#define	RCC_BDCR_LSESYSRDY_Pos (11U)

#define	RCC_BDCR_LSESYSRDY_Msk (0x1UL << RCC_BDCR_LSESYSRDY_Pos)

#define	RCC_BDCR_LSESYSRDY RCC_BDCR_LSESYSRDY_Msk

#define	RCC_BDCR_RTCEN_Pos (15U)

#define	RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)

#define	RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk

#define	RCC_BDCR_BDRST_Pos (16U)

#define	RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)

#define	RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk

#define	RCC_BDCR_LSCOEN_Pos (24U)

#define	RCC_BDCR_LSCOEN_Msk (0x1UL << RCC_BDCR_LSCOEN_Pos)

#define	RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk

#define	RCC_BDCR_LSCOSEL_Pos (25U)

#define	RCC_BDCR_LSCOSEL_Msk (0x1UL << RCC_BDCR_LSCOSEL_Pos)

#define	RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk

#define	RCC_CSR_LSION_Pos (0U)

#define	RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)

#define	RCC_CSR_LSION RCC_CSR_LSION_Msk

#define	RCC_CSR_LSIRDY_Pos (1U)

#define	RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)

#define	RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk

#define	RCC_CSR_LSIPRE_Pos (4U)

#define	RCC_CSR_LSIPRE_Msk (0x1UL << RCC_CSR_LSIPRE_Pos)

#define	RCC_CSR_LSIPRE RCC_CSR_LSIPRE_Msk

#define	RCC_CSR_MSISRANGE_Pos (8U)

#define	RCC_CSR_MSISRANGE_Msk (0xFUL << RCC_CSR_MSISRANGE_Pos)

#define	RCC_CSR_MSISRANGE RCC_CSR_MSISRANGE_Msk

#define	RCC_CSR_MSISRANGE_1 (0x4UL << RCC_CSR_MSISRANGE_Pos)

#define	RCC_CSR_MSISRANGE_2 (0x5UL << RCC_CSR_MSISRANGE_Pos)

#define	RCC_CSR_MSISRANGE_4 (0x6UL << RCC_CSR_MSISRANGE_Pos)

#define	RCC_CSR_MSISRANGE_8 (0x7UL << RCC_CSR_MSISRANGE_Pos)

#define	RCC_CSR_RFRSTF_Pos (14U)

#define	RCC_CSR_RFRSTF_Msk (0x1UL << RCC_CSR_RFRSTF_Pos)

#define	RCC_CSR_RFRSTF RCC_CSR_RFRSTF_Msk

#define	RCC_CSR_RFRST_Pos (15U)

#define	RCC_CSR_RFRST_Msk (0x1UL << RCC_CSR_RFRST_Pos)

#define	RCC_CSR_RFRST RCC_CSR_RFRST_Msk

#define	RCC_CSR_RMVF_Pos (23U)

#define	RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos)

#define	RCC_CSR_RMVF RCC_CSR_RMVF_Msk

#define	RCC_CSR_RFILARSTF_Pos (24U)

#define	RCC_CSR_RFILARSTF_Msk (0x1UL << RCC_CSR_RFILARSTF_Pos)

#define	RCC_CSR_RFILARSTF RCC_CSR_RFILARSTF_Msk

#define	RCC_CSR_OBLRSTF_Pos (25U)

#define	RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos)

#define	RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk

#define	RCC_CSR_PINRSTF_Pos (26U)

#define	RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos)

#define	RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk

#define	RCC_CSR_BORRSTF_Pos (27U)

#define	RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos)

#define	RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk

#define	RCC_CSR_SFTRSTF_Pos (28U)

#define	RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos)

#define	RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk

#define	RCC_CSR_IWDGRSTF_Pos (29U)

#define	RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos)

#define	RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk

#define	RCC_CSR_WWDGRSTF_Pos (30U)

#define	RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos)

#define	RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk

#define	RCC_CSR_LPWRRSTF_Pos (31U)

#define	RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos)

#define	RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk

#define	RCC_EXTCFGR_SHDHPRE_Pos (0U)

#define	RCC_EXTCFGR_SHDHPRE_Msk (0xFUL << RCC_EXTCFGR_SHDHPRE_Pos)

#define	RCC_EXTCFGR_SHDHPRE RCC_EXTCFGR_SHDHPRE_Msk

#define	RCC_EXTCFGR_SHDHPRE_0 (0x1UL << RCC_EXTCFGR_SHDHPRE_Pos)

#define	RCC_EXTCFGR_SHDHPRE_1 (0x2UL << RCC_EXTCFGR_SHDHPRE_Pos)

#define	RCC_EXTCFGR_SHDHPRE_2 (0x4UL << RCC_EXTCFGR_SHDHPRE_Pos)

#define	RCC_EXTCFGR_SHDHPRE_3 (0x8UL << RCC_EXTCFGR_SHDHPRE_Pos)

#define	RCC_EXTCFGR_C2HPRE_Pos (4U)

#define	RCC_EXTCFGR_C2HPRE_Msk (0xFUL << RCC_EXTCFGR_C2HPRE_Pos

#define	RCC_EXTCFGR_C2HPRE RCC_EXTCFGR_C2HPRE_Msk

#define	RCC_EXTCFGR_C2HPRE_0 (0x1UL << RCC_EXTCFGR_C2HPRE_Pos

#define	RCC_EXTCFGR_C2HPRE_1 (0x2UL << RCC_EXTCFGR_C2HPRE_Pos

#define	RCC_EXTCFGR_C2HPRE_2 (0x4UL << RCC_EXTCFGR_C2HPRE_Pos

#define	RCC_EXTCFGR_C2HPRE_3 (0x8UL << RCC_EXTCFGR_C2HPRE_Pos

#define	RCC_EXTCFGR_SHDHPREF_Pos (16U)

#define	RCC_EXTCFGR_SHDHPREF_Msk (0x1UL << RCC_EXTCFGR_SHDHPREF_Pos

#define	RCC_EXTCFGR_SHDHPREF RCC_EXTCFGR_SHDHPREF_Msk

#define	RCC_EXTCFGR_C2HPREF_Pos (17U)

#define	RCC_EXTCFGR_C2HPREF_Msk (0x1UL << RCC_EXTCFGR_C2HPREF_Pos

#define	RCC_EXTCFGR_C2HPREF RCC_EXTCFGR_C2HPREF_Msk

#define	RCC_C2AHB1ENR_DMA1EN_Pos (0U)

#define	RCC_C2AHB1ENR_DMA1EN_Msk (0x1UL << RCC_C2AHB1ENR_DMA1EN_Pos

#define	RCC_C2AHB1ENR_DMA1EN RCC_C2AHB1ENR_DMA1EN_Msk

#define	RCC_C2AHB1ENR_DMA2EN_Pos (1U)

#define	RCC_C2AHB1ENR_DMA2EN_Msk (0x1UL << RCC_C2AHB1ENR_DMA2EN_Pos

#define	RCC_C2AHB1ENR_DMA2EN RCC_C2AHB1ENR_DMA2EN_Msk

#define	RCC_C2AHB1ENR_DMAMUX1EN_Pos (2U)

#define	RCC_C2AHB1ENR_DMAMUX1EN_Msk (0x1UL << RCC_C2AHB1ENR_DMAMUX1EN_Pos

#define	RCC_C2AHB1ENR_DMAMUX1EN RCC_C2AHB1ENR_DMAMUX1EN_Msk

#define	RCC_C2AHB1ENR_CRCEN_Pos (12U)

#define	RCC_C2AHB1ENR_CRCEN_Msk (0x1UL << RCC_C2AHB1ENR_CRCEN_Pos

#define	RCC_C2AHB1ENR_CRCEN RCC_C2AHB1ENR_CRCEN_Msk

#define	RCC_C2AHB2ENR_GPIOAEN_Pos (0U)

#define	RCC_C2AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_C2AHB2ENR_GPIOAEN_Pos

#define	RCC_C2AHB2ENR_GPIOAEN RCC_C2AHB2ENR_GPIOAEN_Msk

#define	RCC_C2AHB2ENR_GPIOBEN_Pos (1U)

#define	RCC_C2AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_C2AHB2ENR_GPIOBEN_Pos

#define	RCC_C2AHB2ENR_GPIOBEN RCC_C2AHB2ENR_GPIOBEN_Msk

#define	RCC_C2AHB2ENR_GPIOCEN_Pos (2U)

#define	RCC_C2AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_C2AHB2ENR_GPIOCEN_Pos

#define	RCC_C2AHB2ENR_GPIOCEN RCC_C2AHB2ENR_GPIOCEN_Msk

#define	RCC_C2AHB2ENR_GPIOHEN_Pos (7U)

#define	RCC_C2AHB2ENR_GPIOHEN_Msk (0x1UL << RCC_C2AHB2ENR_GPIOHEN_Pos

#define	RCC_C2AHB2ENR_GPIOHEN RCC_C2AHB2ENR_GPIOHEN_Msk

#define	RCC_C2AHB3ENR_PKAEN_Pos (16U)

#define	RCC_C2AHB3ENR_PKAEN_Msk (0x1UL << RCC_C2AHB3ENR_PKAEN_Pos)

#define	RCC_C2AHB3ENR_PKAEN RCC_C2AHB3ENR_PKAEN_Msk

#define	RCC_C2AHB3ENR_AESEN_Pos (17U)

#define	RCC_C2AHB3ENR_AESEN_Msk (0x1UL << RCC_C2AHB3ENR_AESEN_Pos

#define	RCC_C2AHB3ENR_AESEN RCC_C2AHB3ENR_AESEN_Msk

#define	RCC_C2AHB3ENR_RNGEN_Pos (18U)

#define	RCC_C2AHB3ENR_RNGEN_Msk (0x1UL << RCC_C2AHB3ENR_RNGEN_Pos

#define	RCC_C2AHB3ENR_RNGEN RCC_C2AHB3ENR_RNGEN_Msk

#define	RCC_C2AHB3ENR_HSEMEN_Pos (19U)

#define	RCC_C2AHB3ENR_HSEMEN_Msk (0x1UL << RCC_C2AHB3ENR_HSEMEN_Pos

#define	RCC_C2AHB3ENR_HSEMEN RCC_C2AHB3ENR_HSEMEN_Msk

#define	RCC_C2AHB3ENR_IPCCEN_Pos (20U)

#define	RCC_C2AHB3ENR_IPCCEN_Msk (0x1UL << RCC_C2AHB3ENR_IPCCEN_Pos

#define	RCC_C2AHB3ENR_IPCCEN RCC_C2AHB3ENR_IPCCEN_Msk

#define	RCC_C2AHB3ENR_FLASHEN_Pos (25U)

#define	RCC_C2AHB3ENR_FLASHEN_Msk (0x1UL << RCC_C2AHB3ENR_FLASHEN_Pos

#define	RCC_C2AHB3ENR_FLASHEN RCC_C2AHB3ENR_FLASHEN_Msk

#define	RCC_C2APB1ENR1_TIM2EN_Pos (0U)

#define	RCC_C2APB1ENR1_TIM2EN_Msk (0x1UL << RCC_C2APB1ENR1_TIM2EN_Pos

#define	RCC_C2APB1ENR1_TIM2EN RCC_C2APB1ENR1_TIM2EN_Msk

#define	RCC_C2APB1ENR1_RTCAPBEN_Pos (10U)

#define	RCC_C2APB1ENR1_RTCAPBEN_Msk (0x1UL << RCC_C2APB1ENR1_RTCAPBEN_Pos

#define	RCC_C2APB1ENR1_RTCAPBEN RCC_C2APB1ENR1_RTCAPBEN_Msk

#define	RCC_C2APB1ENR1_SPI2EN_Pos (14U)

#define	RCC_C2APB1ENR1_SPI2EN_Msk (0x1UL << RCC_C2APB1ENR1_SPI2EN_Pos

#define	RCC_C2APB1ENR1_SPI2EN RCC_C2APB1ENR1_SPI2EN_Msk

#define	RCC_C2APB1ENR1_USART2EN_Pos (17U)

#define	RCC_C2APB1ENR1_USART2EN_Msk (0x1UL << RCC_C2APB1ENR1_USART2EN_Pos

#define	RCC_C2APB1ENR1_USART2EN RCC_C2APB1ENR1_USART2EN_Msk

#define	RCC_C2APB1ENR1_I2C1EN_Pos (21U)

#define	RCC_C2APB1ENR1_I2C1EN_Msk (0x1UL << RCC_C2APB1ENR1_I2C1EN_Pos

#define	RCC_C2APB1ENR1_I2C1EN RCC_C2APB1ENR1_I2C1EN_Msk

#define	RCC_C2APB1ENR1_I2C2EN_Pos (22U)

#define	RCC_C2APB1ENR1_I2C2EN_Msk (0x1UL << RCC_C2APB1ENR1_I2C2EN_Pos

#define	RCC_C2APB1ENR1_I2C2EN RCC_C2APB1ENR1_I2C2EN_Msk

#define	RCC_C2APB1ENR1_I2C3EN_Pos (23U)

#define	RCC_C2APB1ENR1_I2C3EN_Msk (0x1UL << RCC_C2APB1ENR1_I2C3EN_Pos

#define	RCC_C2APB1ENR1_I2C3EN RCC_C2APB1ENR1_I2C3EN_Msk

#define	RCC_C2APB1ENR1_DACEN_Pos (29U)

#define	RCC_C2APB1ENR1_DACEN_Msk (0x1UL << RCC_C2APB1ENR1_DACEN_Pos

#define	RCC_C2APB1ENR1_DACEN RCC_C2APB1ENR1_DACEN_Msk

#define	RCC_C2APB1ENR1_LPTIM1EN_Pos (31U)

#define	RCC_C2APB1ENR1_LPTIM1EN_Msk (0x1UL << RCC_C2APB1ENR1_LPTIM1EN_Pos

#define	RCC_C2APB1ENR1_LPTIM1EN RCC_C2APB1ENR1_LPTIM1EN_Msk

#define	RCC_C2APB1ENR2_LPUART1EN_Pos (0U)

#define	RCC_C2APB1ENR2_LPUART1EN_Msk (0x1UL << RCC_C2APB1ENR2_LPUART1EN_Pos

#define	RCC_C2APB1ENR2_LPUART1EN RCC_C2APB1ENR2_LPUART1EN_Msk

#define	RCC_C2APB1ENR2_LPTIM2EN_Pos (5U)

#define	RCC_C2APB1ENR2_LPTIM2EN_Msk (0x1UL << RCC_C2APB1ENR2_LPTIM2EN_Pos

#define	RCC_C2APB1ENR2_LPTIM2EN RCC_C2APB1ENR2_LPTIM2EN_Msk

#define	RCC_C2APB1ENR2_LPTIM3EN_Pos (6U)

#define	RCC_C2APB1ENR2_LPTIM3EN_Msk (0x1UL << RCC_C2APB1ENR2_LPTIM3EN_Pos

#define	RCC_C2APB1ENR2_LPTIM3EN RCC_C2APB1ENR2_LPTIM3EN_Msk

#define	RCC_C2APB2ENR_ADCEN_Pos (9U)

#define	RCC_C2APB2ENR_ADCEN_Msk (0x1UL << RCC_C2APB2ENR_ADCEN_Pos

#define	RCC_C2APB2ENR_ADCEN RCC_C2APB2ENR_ADCEN_Msk

#define	RCC_C2APB2ENR_TIM1EN_Pos (11U)

#define	RCC_C2APB2ENR_TIM1EN_Msk (0x1UL << RCC_C2APB2ENR_TIM1EN_Pos

#define	RCC_C2APB2ENR_TIM1EN RCC_C2APB2ENR_TIM1EN_Msk

#define	RCC_C2APB2ENR_SPI1EN_Pos (12U)

#define	RCC_C2APB2ENR_SPI1EN_Msk (0x1UL << RCC_C2APB2ENR_SPI1EN_Pos

#define	RCC_C2APB2ENR_SPI1EN RCC_C2APB2ENR_SPI1EN_Msk

#define	RCC_C2APB2ENR_USART1EN_Pos (14U)

#define	RCC_C2APB2ENR_USART1EN_Msk (0x1UL << RCC_C2APB2ENR_USART1EN_Pos

#define	RCC_C2APB2ENR_USART1EN RCC_C2APB2ENR_USART1EN_Msk

#define	RCC_C2APB2ENR_TIM16EN_Pos (17U)

#define	RCC_C2APB2ENR_TIM16EN_Msk (0x1UL << RCC_C2APB2ENR_TIM16EN_Pos

#define	RCC_C2APB2ENR_TIM16EN RCC_C2APB2ENR_TIM16EN_Msk

#define	RCC_C2APB2ENR_TIM17EN_Pos (18U)

#define	RCC_C2APB2ENR_TIM17EN_Msk (0x1UL << RCC_C2APB2ENR_TIM17EN_Pos

#define	RCC_C2APB2ENR_TIM17EN RCC_C2APB2ENR_TIM17EN_Msk

#define	RCC_C2APB2ENR_SAI1EN_Pos (21U)

#define	RCC_C2APB2ENR_SAI1EN_Msk (0x1UL << RCC_C2APB2ENR_SAI1EN_Pos

#define	RCC_C2APB2ENR_SAI1EN RCC_C2APB2ENR_SAI1EN_Msk

#define	RCC_C2APB3ENR_SUBGHZSPIEN_Pos (0U)

#define	RCC_C2APB3ENR_SUBGHZSPIEN_Msk (0x1UL << RCC_C2APB3ENR_SUBGHZSPIEN_Pos

#define	RCC_C2APB3ENR_SUBGHZSPIEN RCC_C2APB3ENR_SUBGHZSPIEN_Msk

#define	RCC_C2AHB1SMENR_DMA1SMEN_Pos (0U)

#define	RCC_C2AHB1SMENR_DMA1SMEN_Msk (0x1UL << RCC_C2AHB1SMENR_DMA1SMEN_Pos

#define	RCC_C2AHB1SMENR_DMA1SMEN RCC_C2AHB1SMENR_DMA1SMEN_Msk

#define	RCC_C2AHB1SMENR_DMA2SMEN_Pos (1U)

#define	RCC_C2AHB1SMENR_DMA2SMEN_Msk (0x1UL << RCC_C2AHB1SMENR_DMA2SMEN_Pos

#define	RCC_C2AHB1SMENR_DMA2SMEN RCC_C2AHB1SMENR_DMA2SMEN_Msk

#define	RCC_C2AHB1SMENR_DMAMUX1SMEN_Pos (2U)

#define	RCC_C2AHB1SMENR_DMAMUX1SMEN_Msk (0x1UL << RCC_C2AHB1SMENR_DMAMUX1SMEN_Pos

#define	RCC_C2AHB1SMENR_DMAMUX1SMEN RCC_C2AHB1SMENR_DMAMUX1SMEN_Msk

#define	RCC_C2AHB1SMENR_CRCSMEN_Pos (12U)

#define	RCC_C2AHB1SMENR_CRCSMEN_Msk (0x1UL << RCC_C2AHB1SMENR_CRCSMEN_Pos

#define	RCC_C2AHB1SMENR_CRCSMEN RCC_C2AHB1SMENR_CRCSMEN_Msk

#define	RCC_C2AHB2SMENR_GPIOASMEN_Pos (0U)

#define	RCC_C2AHB2SMENR_GPIOASMEN_Msk (0x1UL << RCC_C2AHB2SMENR_GPIOASMEN_Pos

#define	RCC_C2AHB2SMENR_GPIOASMEN RCC_C2AHB2SMENR_GPIOASMEN_Msk

#define	RCC_C2AHB2SMENR_GPIOBSMEN_Pos (1U)

#define	RCC_C2AHB2SMENR_GPIOBSMEN_Msk (0x1UL << RCC_C2AHB2SMENR_GPIOBSMEN_Pos

#define	RCC_C2AHB2SMENR_GPIOBSMEN RCC_C2AHB2SMENR_GPIOBSMEN_Msk

#define	RCC_C2AHB2SMENR_GPIOCSMEN_Pos (2U)

#define	RCC_C2AHB2SMENR_GPIOCSMEN_Msk (0x1UL << RCC_C2AHB2SMENR_GPIOCSMEN_Pos

#define	RCC_C2AHB2SMENR_GPIOCSMEN RCC_C2AHB2SMENR_GPIOCSMEN_Msk

#define	RCC_C2AHB2SMENR_GPIOHSMEN_Pos (7U)

#define	RCC_C2AHB2SMENR_GPIOHSMEN_Msk (0x1UL << RCC_C2AHB2SMENR_GPIOHSMEN_Pos

#define	RCC_C2AHB2SMENR_GPIOHSMEN RCC_C2AHB2SMENR_GPIOHSMEN_Msk

#define	RCC_C2AHB3SMENR_PKASMEN_Pos (16U)

#define	RCC_C2AHB3SMENR_PKASMEN_Msk (0x1UL << RCC_C2AHB3SMENR_PKASMEN_Pos)

#define	RCC_C2AHB3SMENR_PKASMEN RCC_C2AHB3SMENR_PKASMEN_Msk

#define	RCC_C2AHB3SMENR_AESSMEN_Pos (17U)

#define	RCC_C2AHB3SMENR_AESSMEN_Msk (0x1UL << RCC_C2AHB3SMENR_AESSMEN_Pos

#define	RCC_C2AHB3SMENR_AESSMEN RCC_C2AHB3SMENR_AESSMEN_Msk

#define	RCC_C2AHB3SMENR_RNGSMEN_Pos (18U)

#define	RCC_C2AHB3SMENR_RNGSMEN_Msk (0x1UL << RCC_C2AHB3SMENR_RNGSMEN_Pos

#define	RCC_C2AHB3SMENR_RNGSMEN RCC_C2AHB3SMENR_RNGSMEN_Msk

#define	RCC_C2AHB3SMENR_SRAM1SMEN_Pos (23U)

#define	RCC_C2AHB3SMENR_SRAM1SMEN_Msk (0x1UL << RCC_C2AHB3SMENR_SRAM1SMEN_Pos

#define	RCC_C2AHB3SMENR_SRAM1SMEN RCC_C2AHB3SMENR_SRAM1SMEN_Msk

#define	RCC_C2AHB3SMENR_SRAM2SMEN_Pos (24U)

#define	RCC_C2AHB3SMENR_SRAM2SMEN_Msk (0x1UL << RCC_C2AHB3SMENR_SRAM2SMEN_Pos

#define	RCC_C2AHB3SMENR_SRAM2SMEN RCC_C2AHB3SMENR_SRAM2SMEN_Msk

#define	RCC_C2AHB3SMENR_FLASHSMEN_Pos (25U)

#define	RCC_C2AHB3SMENR_FLASHSMEN_Msk (0x1UL << RCC_C2AHB3SMENR_FLASHSMEN_Pos

#define	RCC_C2AHB3SMENR_FLASHSMEN RCC_C2AHB3SMENR_FLASHSMEN_Msk

#define	RCC_C2APB1SMENR1_TIM2SMEN_Pos (0U)

#define	RCC_C2APB1SMENR1_TIM2SMEN_Msk (0x1UL << RCC_C2APB1SMENR1_TIM2SMEN_Pos

#define	RCC_C2APB1SMENR1_TIM2SMEN RCC_C2APB1SMENR1_TIM2SMEN_Msk

#define	RCC_C2APB1SMENR1_RTCAPBSMEN_Pos (10U)

#define	RCC_C2APB1SMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_C2APB1SMENR1_RTCAPBSMEN_Pos

#define	RCC_C2APB1SMENR1_RTCAPBSMEN RCC_C2APB1SMENR1_RTCAPBSMEN_Msk

#define	RCC_C2APB1SMENR1_SPI2SMEN_Pos (14U)

#define	RCC_C2APB1SMENR1_SPI2SMEN_Msk (0x1UL << RCC_C2APB1SMENR1_SPI2SMEN_Pos

#define	RCC_C2APB1SMENR1_SPI2SMEN RCC_C2APB1SMENR1_SPI2SMEN_Msk

#define	RCC_C2APB1SMENR1_USART2SMEN_Pos (17U)

#define	RCC_C2APB1SMENR1_USART2SMEN_Msk (0x1UL << RCC_C2APB1SMENR1_USART2SMEN_Pos

#define	RCC_C2APB1SMENR1_USART2SMEN RCC_C2APB1SMENR1_USART2SMEN_Msk

#define	RCC_C2APB1SMENR1_I2C1SMEN_Pos (21U)

#define	RCC_C2APB1SMENR1_I2C1SMEN_Msk (0x1UL << RCC_C2APB1SMENR1_I2C1SMEN_Pos

#define	RCC_C2APB1SMENR1_I2C1SMEN RCC_C2APB1SMENR1_I2C1SMEN_Msk

#define	RCC_C2APB1SMENR1_I2C2SMEN_Pos (22U)

#define	RCC_C2APB1SMENR1_I2C2SMEN_Msk (0x1UL << RCC_C2APB1SMENR1_I2C2SMEN_Pos

#define	RCC_C2APB1SMENR1_I2C2SMEN RCC_C2APB1SMENR1_I2C2SMEN_Msk

#define	RCC_C2APB1SMENR1_I2C3SMEN_Pos (23U)

#define	RCC_C2APB1SMENR1_I2C3SMEN_Msk (0x1UL << RCC_C2APB1SMENR1_I2C3SMEN_Pos

#define	RCC_C2APB1SMENR1_I2C3SMEN RCC_C2APB1SMENR1_I2C3SMEN_Msk

#define	RCC_C2APB1SMENR1_DACSMEN_Pos (29U)

#define	RCC_C2APB1SMENR1_DACSMEN_Msk (0x1UL << RCC_C2APB1SMENR1_DACSMEN_Pos

#define	RCC_C2APB1SMENR1_DACSMEN RCC_C2APB1SMENR1_DACSMEN_Msk

#define	RCC_C2APB1SMENR1_LPTIM1SMEN_Pos (31U)

#define	RCC_C2APB1SMENR1_LPTIM1SMEN_Msk (0x1UL << RCC_C2APB1SMENR1_LPTIM1SMEN_Pos

#define	RCC_C2APB1SMENR1_LPTIM1SMEN RCC_C2APB1SMENR1_LPTIM1SMEN_Msk

#define	RCC_C2APB1SMENR2_LPUART1SMEN_Pos (0U)

#define	RCC_C2APB1SMENR2_LPUART1SMEN_Msk (0x1UL << RCC_C2APB1SMENR2_LPUART1SMEN_Pos

#define	RCC_C2APB1SMENR2_LPUART1SMEN RCC_C2APB1SMENR2_LPUART1SMEN_Msk

#define	RCC_C2APB1SMENR2_LPTIM2SMEN_Pos (5U)

#define	RCC_C2APB1SMENR2_LPTIM2SMEN_Msk (0x1UL << RCC_C2APB1SMENR2_LPTIM2SMEN_Pos

#define	RCC_C2APB1SMENR2_LPTIM2SMEN RCC_C2APB1SMENR2_LPTIM2SMEN_Msk

#define	RCC_C2APB1SMENR2_LPTIM3SMEN_Pos (6U)

#define	RCC_C2APB1SMENR2_LPTIM3SMEN_Msk (0x1UL << RCC_C2APB1SMENR2_LPTIM3SMEN_Pos

#define	RCC_C2APB1SMENR2_LPTIM3SMEN RCC_C2APB1SMENR2_LPTIM3SMEN_Msk

#define	RCC_C2APB2SMENR_ADCSMEN_Pos (9U)

#define	RCC_C2APB2SMENR_ADCSMEN_Msk (0x1UL << RCC_C2APB2SMENR_ADCSMEN_Pos

#define	RCC_C2APB2SMENR_ADCSMEN RCC_C2APB2SMENR_ADCSMEN_Msk

#define	RCC_C2APB2SMENR_TIM1SMEN_Pos (11U)

#define	RCC_C2APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_C2APB2SMENR_TIM1SMEN_Pos

#define	RCC_C2APB2SMENR_TIM1SMEN RCC_C2APB2SMENR_TIM1SMEN_Msk

#define	RCC_C2APB2SMENR_SPI1SMEN_Pos (12U)

#define	RCC_C2APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_C2APB2SMENR_SPI1SMEN_Pos

#define	RCC_C2APB2SMENR_SPI1SMEN RCC_C2APB2SMENR_SPI1SMEN_Msk

#define	RCC_C2APB2SMENR_USART1SMEN_Pos (14U)

#define	RCC_C2APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_C2APB2SMENR_USART1SMEN_Pos

#define	RCC_C2APB2SMENR_USART1SMEN RCC_C2APB2SMENR_USART1SMEN_Msk

#define	RCC_C2APB2SMENR_TIM16SMEN_Pos (17U)

#define	RCC_C2APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_C2APB2SMENR_TIM16SMEN_Pos

#define	RCC_C2APB2SMENR_TIM16SMEN RCC_C2APB2SMENR_TIM16SMEN_Msk

#define	RCC_C2APB2SMENR_TIM17SMEN_Pos (18U)

#define	RCC_C2APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_C2APB2SMENR_TIM17SMEN_Pos

#define	RCC_C2APB2SMENR_TIM17SMEN RCC_C2APB2SMENR_TIM17SMEN_Msk

#define	RCC_C2APB3SMENR_SUBGHZSPISMEN_Pos (0U)

#define	RCC_C2APB3SMENR_SUBGHZSPISMEN_Msk (0x1UL << RCC_C2APB3SMENR_SUBGHZSPISMEN_Pos

#define	RCC_C2APB3SMENR_SUBGHZSPISMEN RCC_C2APB3SMENR_SUBGHZSPISMEN_Msk

#define	RNG_VER_3_2

#define	RNG_CR_RNGEN_Pos (2U)

#define	RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos)

#define	RNG_CR_RNGEN RNG_CR_RNGEN_Msk

#define	RNG_CR_IE_Pos (3U)

#define	RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos)

#define	RNG_CR_IE RNG_CR_IE_Msk

#define	RNG_CR_CED_Pos (5U)

#define	RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos)

#define	RNG_CR_CED RNG_CR_CED_Msk

#define	RNG_CR_RNG_CONFIG3_Pos (8U)

#define	RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos)

#define	RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk

#define	RNG_CR_NISTC_Pos (12U)

#define	RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos)

#define	RNG_CR_NISTC RNG_CR_NISTC_Msk

#define	RNG_CR_RNG_CONFIG2_Pos (13U)

#define	RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos)

#define	RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk

#define	RNG_CR_CLKDIV_Pos (16U)

#define	RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos)

#define	RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk

#define	RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos)

#define	RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos)

#define	RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos)

#define	RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos)

#define	RNG_CR_RNG_CONFIG1_Pos (20U)

#define	RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos)

#define	RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk

#define	RNG_CR_CONDRST_Pos (30U)

#define	RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos)

#define	RNG_CR_CONDRST RNG_CR_CONDRST_Msk

#define	RNG_CR_CONFIGLOCK_Pos (31U)

#define	RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos)

#define	RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk

#define	RNG_SR_DRDY_Pos (0U)

#define	RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos)

#define	RNG_SR_DRDY RNG_SR_DRDY_Msk

#define	RNG_SR_CECS_Pos (1U)

#define	RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos)

#define	RNG_SR_CECS RNG_SR_CECS_Msk

#define	RNG_SR_SECS_Pos (2U)

#define	RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos)

#define	RNG_SR_SECS RNG_SR_SECS_Msk

#define	RNG_SR_CEIS_Pos (5U)

#define	RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos)

#define	RNG_SR_CEIS RNG_SR_CEIS_Msk

#define	RNG_SR_SEIS_Pos (6U)

#define	RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos)

#define	RNG_SR_SEIS RNG_SR_SEIS_Msk

#define	RNG_DR_RNDATA_Pos (0U)

#define	RNG_DR_RNDATA_Msk (0xFFFFFFFFUL << RNG_DR_RNDATA_Pos)

#define	RNG_DR_RNDATA RNG_DR_RNDATA_Msk

#define	RNG_HTCR_HTCFG_Pos (0U)

#define	RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos)

#define	RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk

#define	RTC_TR_PM_Pos (22U)

#define	RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)

#define	RTC_TR_PM RTC_TR_PM_Msk

#define	RTC_TR_HT_Pos (20U)

#define	RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)

#define	RTC_TR_HT RTC_TR_HT_Msk

#define	RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)

#define	RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)

#define	RTC_TR_HU_Pos (16U)

#define	RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)

#define	RTC_TR_HU RTC_TR_HU_Msk

#define	RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)

#define	RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)

#define	RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)

#define	RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)

#define	RTC_TR_MNT_Pos (12U)

#define	RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)

#define	RTC_TR_MNT RTC_TR_MNT_Msk

#define	RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)

#define	RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)

#define	RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)

#define	RTC_TR_MNU_Pos (8U)

#define	RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)

#define	RTC_TR_MNU RTC_TR_MNU_Msk

#define	RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)

#define	RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)

#define	RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)

#define	RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)

#define	RTC_TR_ST_Pos (4U)

#define	RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)

#define	RTC_TR_ST RTC_TR_ST_Msk

#define	RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)

#define	RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)

#define	RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)

#define	RTC_TR_SU_Pos (0U)

#define	RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)

#define	RTC_TR_SU RTC_TR_SU_Msk

#define	RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)

#define	RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)

#define	RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)

#define	RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)

#define	RTC_DR_YT_Pos (20U)

#define	RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)

#define	RTC_DR_YT RTC_DR_YT_Msk

#define	RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)

#define	RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)

#define	RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)

#define	RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)

#define	RTC_DR_YU_Pos (16U)

#define	RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)

#define	RTC_DR_YU RTC_DR_YU_Msk

#define	RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)

#define	RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)

#define	RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)

#define	RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)

#define	RTC_DR_WDU_Pos (13U)

#define	RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)

#define	RTC_DR_WDU RTC_DR_WDU_Msk

#define	RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)

#define	RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)

#define	RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)

#define	RTC_DR_MT_Pos (12U)

#define	RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)

#define	RTC_DR_MT RTC_DR_MT_Msk

#define	RTC_DR_MU_Pos (8U)

#define	RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)

#define	RTC_DR_MU RTC_DR_MU_Msk

#define	RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)

#define	RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)

#define	RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)

#define	RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)

#define	RTC_DR_DT_Pos (4U)

#define	RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)

#define	RTC_DR_DT RTC_DR_DT_Msk

#define	RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)

#define	RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)

#define	RTC_DR_DU_Pos (0U)

#define	RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)

#define	RTC_DR_DU RTC_DR_DU_Msk

#define	RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)

#define	RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)

#define	RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)

#define	RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)

#define	RTC_SSR_SS_Pos (0U)

#define	RTC_SSR_SS_Msk (0xFFFFFFFFUL << RTC_SSR_SS_Pos)

#define	RTC_SSR_SS RTC_SSR_SS_Msk

#define	RTC_ICSR_RECALPF_Pos (16U)

#define	RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos)

#define	RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk

#define	RTC_ICSR_BCDU_Pos (10U)

#define	RTC_ICSR_BCDU_Msk (0x7UL << RTC_ICSR_BCDU_Pos)

#define	RTC_ICSR_BCDU RTC_ICSR_BCDU_Msk

#define	RTC_ICSR_BCDU_0 (0x1UL << RTC_ICSR_BCDU_Pos)

#define	RTC_ICSR_BCDU_1 (0x2UL << RTC_ICSR_BCDU_Pos)

#define	RTC_ICSR_BCDU_2 (0x4UL << RTC_ICSR_BCDU_Pos)

#define	RTC_ICSR_BIN_Pos (8U)

#define	RTC_ICSR_BIN_Msk (0x3UL << RTC_ICSR_BIN_Pos)

#define	RTC_ICSR_BIN RTC_ICSR_BIN_Msk

#define	RTC_ICSR_BIN_0 (0x1UL << RTC_ICSR_BIN_Pos)

#define	RTC_ICSR_BIN_1 (0x2UL << RTC_ICSR_BIN_Pos)

#define	RTC_ICSR_INIT_Pos (7U)

#define	RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos)

#define	RTC_ICSR_INIT RTC_ICSR_INIT_Msk

#define	RTC_ICSR_INITF_Pos (6U)

#define	RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos)

#define	RTC_ICSR_INITF RTC_ICSR_INITF_Msk

#define	RTC_ICSR_RSF_Pos (5U)

#define	RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos)

#define	RTC_ICSR_RSF RTC_ICSR_RSF_Msk

#define	RTC_ICSR_INITS_Pos (4U)

#define	RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos)

#define	RTC_ICSR_INITS RTC_ICSR_INITS_Msk

#define	RTC_ICSR_SHPF_Pos (3U)

#define	RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos)

#define	RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk

#define	RTC_ICSR_WUTWF_Pos (2U)

#define	RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos)

#define	RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk

#define	RTC_PRER_PREDIV_A_Pos (16U)

#define	RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)

#define	RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk

#define	RTC_PRER_PREDIV_S_Pos (0U)

#define	RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)

#define	RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk

#define	RTC_WUTR_WUTOCLR_Pos (16U)

#define	RTC_WUTR_WUTOCLR_Msk (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos)

#define	RTC_WUTR_WUTOCLR RTC_WUTR_WUTOCLR_Msk

#define	RTC_WUTR_WUT_Pos (0U)

#define	RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos)

#define	RTC_WUTR_WUT RTC_WUTR_WUT_Msk

#define	RTC_CR_OUT2EN_Pos (31U)

#define	RTC_CR_OUT2EN_Msk (0x1UL << RTC_CR_OUT2EN_Pos)

#define	RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk

#define	RTC_CR_TAMPALRM_TYPE_Pos (30U)

#define	RTC_CR_TAMPALRM_TYPE_Msk (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos)

#define	RTC_CR_TAMPALRM_TYPE RTC_CR_TAMPALRM_TYPE_Msk

#define	RTC_CR_TAMPALRM_PU_Pos (29U)

#define	RTC_CR_TAMPALRM_PU_Msk (0x1UL << RTC_CR_TAMPALRM_PU_Pos)

#define	RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk

#define	RTC_CR_TAMPOE_Pos (26U)

#define	RTC_CR_TAMPOE_Msk (0x1UL << RTC_CR_TAMPOE_Pos)

#define	RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk

#define	RTC_CR_TAMPTS_Pos (25U)

#define	RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos)

#define	RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk

#define	RTC_CR_ITSE_Pos (24U)

#define	RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos)

#define	RTC_CR_ITSE RTC_CR_ITSE_Msk

#define	RTC_CR_COE_Pos (23U)

#define	RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)

#define	RTC_CR_COE RTC_CR_COE_Msk

#define	RTC_CR_OSEL_Pos (21U)

#define	RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)

#define	RTC_CR_OSEL RTC_CR_OSEL_Msk

#define	RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)

#define	RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)

#define	RTC_CR_POL_Pos (20U)

#define	RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)

#define	RTC_CR_POL RTC_CR_POL_Msk

#define	RTC_CR_COSEL_Pos (19U)

#define	RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos)

#define	RTC_CR_COSEL RTC_CR_COSEL_Msk

#define	RTC_CR_BKP_Pos (18U)

#define	RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)

#define	RTC_CR_BKP RTC_CR_BKP_Msk

#define	RTC_CR_SUB1H_Pos (17U)

#define	RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)

#define	RTC_CR_SUB1H RTC_CR_SUB1H_Msk

#define	RTC_CR_ADD1H_Pos (16U)

#define	RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)

#define	RTC_CR_ADD1H RTC_CR_ADD1H_Msk

#define	RTC_CR_TSIE_Pos (15U)

#define	RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)

#define	RTC_CR_TSIE RTC_CR_TSIE_Msk

#define	RTC_CR_WUTIE_Pos (14U)

#define	RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos)

#define	RTC_CR_WUTIE RTC_CR_WUTIE_Msk

#define	RTC_CR_ALRBIE_Pos (13U)

#define	RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos)

#define	RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk

#define	RTC_CR_ALRAIE_Pos (12U)

#define	RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)

#define	RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk

#define	RTC_CR_TSE_Pos (11U)

#define	RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)

#define	RTC_CR_TSE RTC_CR_TSE_Msk

#define	RTC_CR_WUTE_Pos (10U)

#define	RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos)

#define	RTC_CR_WUTE RTC_CR_WUTE_Msk

#define	RTC_CR_ALRBE_Pos (9U)

#define	RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos)

#define	RTC_CR_ALRBE RTC_CR_ALRBE_Msk

#define	RTC_CR_ALRAE_Pos (8U)

#define	RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)

#define	RTC_CR_ALRAE RTC_CR_ALRAE_Msk

#define	RTC_CR_SSRUIE_Pos (7U)

#define	RTC_CR_SSRUIE_Msk (0x1UL << RTC_CR_SSRUIE_Pos)

#define	RTC_CR_SSRUIE RTC_CR_SSRUIE_Msk

#define	RTC_CR_FMT_Pos (6U)

#define	RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)

#define	RTC_CR_FMT RTC_CR_FMT_Msk

#define	RTC_CR_BYPSHAD_Pos (5U)

#define	RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos)

#define	RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk

#define	RTC_CR_REFCKON_Pos (4U)

#define	RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)

#define	RTC_CR_REFCKON RTC_CR_REFCKON_Msk

#define	RTC_CR_TSEDGE_Pos (3U)

#define	RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)

#define	RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk

#define	RTC_CR_WUCKSEL_Pos (0U)

#define	RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos)

#define	RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk

#define	RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos)

#define	RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos)

#define	RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos)

#define	RTC_WPR_KEY_Pos (0U)

#define	RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)

#define	RTC_WPR_KEY RTC_WPR_KEY_Msk

#define	RTC_CALR_CALP_Pos (15U)

#define	RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos)

#define	RTC_CALR_CALP RTC_CALR_CALP_Msk

#define	RTC_CALR_CALW8_Pos (14U)

#define	RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos)

#define	RTC_CALR_CALW8 RTC_CALR_CALW8_Msk

#define	RTC_CALR_CALW16_Pos (13U)

#define	RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos)

#define	RTC_CALR_LPCAL RTC_CALR_LPCAL_Msk

#define	RTC_CALR_LPCAL_Pos (12U)

#define	RTC_CALR_LPCAL_Msk (0x1UL << RTC_CALR_LPCAL_Pos)

#define	RTC_CALR_CALW16 RTC_CALR_CALW16_Msk

#define	RTC_CALR_CALM_Pos (0U)

#define	RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM RTC_CALR_CALM_Msk

#define	RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos)

#define	RTC_SHIFTR_ADD1S_Pos (31U)

#define	RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos)

#define	RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk

#define	RTC_SHIFTR_SUBFS_Pos (0U)

#define	RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)

#define	RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk

#define	RTC_TSTR_PM_Pos (22U)

#define	RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)

#define	RTC_TSTR_PM RTC_TSTR_PM_Msk

#define	RTC_TSTR_HT_Pos (20U)

#define	RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)

#define	RTC_TSTR_HT RTC_TSTR_HT_Msk

#define	RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)

#define	RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)

#define	RTC_TSTR_HU_Pos (16U)

#define	RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)

#define	RTC_TSTR_HU RTC_TSTR_HU_Msk

#define	RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)

#define	RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)

#define	RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)

#define	RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)

#define	RTC_TSTR_MNT_Pos (12U)

#define	RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)

#define	RTC_TSTR_MNT RTC_TSTR_MNT_Msk

#define	RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)

#define	RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)

#define	RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)

#define	RTC_TSTR_MNU_Pos (8U)

#define	RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)

#define	RTC_TSTR_MNU RTC_TSTR_MNU_Msk

#define	RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)

#define	RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)

#define	RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)

#define	RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)

#define	RTC_TSTR_ST_Pos (4U)

#define	RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)

#define	RTC_TSTR_ST RTC_TSTR_ST_Msk

#define	RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)

#define	RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)

#define	RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)

#define	RTC_TSTR_SU_Pos (0U)

#define	RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)

#define	RTC_TSTR_SU RTC_TSTR_SU_Msk

#define	RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)

#define	RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)

#define	RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)

#define	RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)

#define	RTC_TSDR_WDU_Pos (13U)

#define	RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)

#define	RTC_TSDR_WDU RTC_TSDR_WDU_Msk

#define	RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)

#define	RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)

#define	RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)

#define	RTC_TSDR_MT_Pos (12U)

#define	RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)

#define	RTC_TSDR_MT RTC_TSDR_MT_Msk

#define	RTC_TSDR_MU_Pos (8U)

#define	RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)

#define	RTC_TSDR_MU RTC_TSDR_MU_Msk

#define	RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)

#define	RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)

#define	RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)

#define	RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)

#define	RTC_TSDR_DT_Pos (4U)

#define	RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)

#define	RTC_TSDR_DT RTC_TSDR_DT_Msk

#define	RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)

#define	RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)

#define	RTC_TSDR_DU_Pos (0U)

#define	RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)

#define	RTC_TSDR_DU RTC_TSDR_DU_Msk

#define	RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)

#define	RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)

#define	RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)

#define	RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)

#define	RTC_TSSSR_SS_Pos (0U)

#define	RTC_TSSSR_SS_Msk (0xFFFFFFFFUL << RTC_TSSSR_SS_Pos)

#define	RTC_TSSSR_SS RTC_TSSSR_SS_Msk

#define	RTC_ALRMAR_MSK4_Pos (31U)

#define	RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)

#define	RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk

#define	RTC_ALRMAR_WDSEL_Pos (30U)

#define	RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)

#define	RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk

#define	RTC_ALRMAR_DT_Pos (28U)

#define	RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)

#define	RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk

#define	RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)

#define	RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)

#define	RTC_ALRMAR_DU_Pos (24U)

#define	RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)

#define	RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk

#define	RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)

#define	RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)

#define	RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)

#define	RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)

#define	RTC_ALRMAR_MSK3_Pos (23U)

#define	RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)

#define	RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk

#define	RTC_ALRMAR_PM_Pos (22U)

#define	RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos)

#define	RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk

#define	RTC_ALRMAR_HT_Pos (20U)

#define	RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)

#define	RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk

#define	RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)

#define	RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)

#define	RTC_ALRMAR_HU_Pos (16U)

#define	RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)

#define	RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk

#define	RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)

#define	RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)

#define	RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)

#define	RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)

#define	RTC_ALRMAR_MSK2_Pos (15U)

#define	RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)

#define	RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk

#define	RTC_ALRMAR_MNT_Pos (12U)

#define	RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)

#define	RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk

#define	RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)

#define	RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)

#define	RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)

#define	RTC_ALRMAR_MNU_Pos (8U)

#define	RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)

#define	RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk

#define	RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)

#define	RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)

#define	RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)

#define	RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)

#define	RTC_ALRMAR_MSK1_Pos (7U)

#define	RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)

#define	RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk

#define	RTC_ALRMAR_ST_Pos (4U)

#define	RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)

#define	RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk

#define	RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)

#define	RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)

#define	RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)

#define	RTC_ALRMAR_SU_Pos (0U)

#define	RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)

#define	RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk

#define	RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)

#define	RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)

#define	RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)

#define	RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)

#define	RTC_ALRMASSR_SSCLR_Pos (31U)

#define	RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos)

#define	RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk

#define	RTC_ALRMASSR_MASKSS_Pos (24U)

#define	RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos)

#define	RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk

#define	RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos)

#define	RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos)

#define	RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos)

#define	RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos)

#define	RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos)

#define	RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos)

#define	RTC_ALRMASSR_SS_Pos (0U)

#define	RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos)

#define	RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk

#define	RTC_ALRMBR_MSK4_Pos (31U)

#define	RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos)

#define	RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk

#define	RTC_ALRMBR_WDSEL_Pos (30U)

#define	RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos)

#define	RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk

#define	RTC_ALRMBR_DT_Pos (28U)

#define	RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos)

#define	RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk

#define	RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos)

#define	RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos)

#define	RTC_ALRMBR_DU_Pos (24U)

#define	RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos)

#define	RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk

#define	RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos)

#define	RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos)

#define	RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos)

#define	RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos)

#define	RTC_ALRMBR_MSK3_Pos (23U)

#define	RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos)

#define	RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk

#define	RTC_ALRMBR_PM_Pos (22U)

#define	RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos)

#define	RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk

#define	RTC_ALRMBR_HT_Pos (20U)

#define	RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos)

#define	RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk

#define	RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos)

#define	RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos)

#define	RTC_ALRMBR_HU_Pos (16U)

#define	RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos)

#define	RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk

#define	RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos)

#define	RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos)

#define	RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos)

#define	RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos)

#define	RTC_ALRMBR_MSK2_Pos (15U)

#define	RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos)

#define	RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk

#define	RTC_ALRMBR_MNT_Pos (12U)

#define	RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos)

#define	RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk

#define	RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos)

#define	RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos)

#define	RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos)

#define	RTC_ALRMBR_MNU_Pos (8U)

#define	RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos)

#define	RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk

#define	RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos)

#define	RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos)

#define	RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)

#define	RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos)

#define	RTC_ALRMBR_MSK1_Pos (7U)

#define	RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos)

#define	RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk

#define	RTC_ALRMBR_ST_Pos (4U)

#define	RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos)

#define	RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk

#define	RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos)

#define	RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos)

#define	RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos)

#define	RTC_ALRMBR_SU_Pos (0U)

#define	RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos)

#define	RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk

#define	RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos)

#define	RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos)

#define	RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos)

#define	RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos)

#define	RTC_ALRMBSSR_SSCLR_Pos (31U)

#define	RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos)

#define	RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk

#define	RTC_ALRMBSSR_MASKSS_Pos (24U)

#define	RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos)

#define	RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk

#define	RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)

#define	RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)

#define	RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)

#define	RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)

#define	RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos)

#define	RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos)

#define	RTC_ALRMBSSR_SS_Pos (0U)

#define	RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)

#define	RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk

#define	RTC_SR_SSRUF_Pos (6U)

#define	RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos)

#define	RTC_SR_SSRUF RTC_SR_SSRUF_Msk

#define	RTC_SR_ITSF_Pos (5U)

#define	RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos)

#define	RTC_SR_ITSF RTC_SR_ITSF_Msk

#define	RTC_SR_TSOVF_Pos (4U)

#define	RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos)

#define	RTC_SR_TSOVF RTC_SR_TSOVF_Msk

#define	RTC_SR_TSF_Pos (3U)

#define	RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos)

#define	RTC_SR_TSF RTC_SR_TSF_Msk

#define	RTC_SR_WUTF_Pos (2U)

#define	RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos)

#define	RTC_SR_WUTF RTC_SR_WUTF_Msk

#define	RTC_SR_ALRBF_Pos (1U)

#define	RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos)

#define	RTC_SR_ALRBF RTC_SR_ALRBF_Msk

#define	RTC_SR_ALRAF_Pos (0U)

#define	RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos)

#define	RTC_SR_ALRAF RTC_SR_ALRAF_Msk

#define	RTC_MISR_SSRUMF_Pos (6U)

#define	RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos)

#define	RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk

#define	RTC_MISR_ITSMF_Pos (5U)

#define	RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos)

#define	RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk

#define	RTC_MISR_TSOVMF_Pos (4U)

#define	RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos)

#define	RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk

#define	RTC_MISR_TSMF_Pos (3U)

#define	RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos)

#define	RTC_MISR_TSMF RTC_MISR_TSMF_Msk

#define	RTC_MISR_WUTMF_Pos (2U)

#define	RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos)

#define	RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk

#define	RTC_MISR_ALRBMF_Pos (1U)

#define	RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos)

#define	RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk

#define	RTC_MISR_ALRAMF_Pos (0U)

#define	RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos)

#define	RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk

#define	RTC_SCR_CSSRUF_Pos (6U)

#define	RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos)

#define	RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk

#define	RTC_SCR_CITSF_Pos (5U)

#define	RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos)

#define	RTC_SCR_CITSF RTC_SCR_CITSF_Msk

#define	RTC_SCR_CTSOVF_Pos (4U)

#define	RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos)

#define	RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk

#define	RTC_SCR_CTSF_Pos (3U)

#define	RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos)

#define	RTC_SCR_CTSF RTC_SCR_CTSF_Msk

#define	RTC_SCR_CWUTF_Pos (2U)

#define	RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos)

#define	RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk

#define	RTC_SCR_CALRBF_Pos (1U)

#define	RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos)

#define	RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk

#define	RTC_SCR_CALRAF_Pos (0U)

#define	RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos)

#define	RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk

#define	RTC_ALRABINR_SS_Pos (0U)

#define	RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos)

#define	RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk

#define	RTC_ALRBBINR_SS_Pos (0U)

#define	RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos)

#define	RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk

#define	SPI_CR1_CPHA_Pos (0U)

#define	SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos)

#define	SPI_CR1_CPHA SPI_CR1_CPHA_Msk

#define	SPI_CR1_CPOL_Pos (1U)

#define	SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos)

#define	SPI_CR1_CPOL SPI_CR1_CPOL_Msk

#define	SPI_CR1_MSTR_Pos (2U)

#define	SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos)

#define	SPI_CR1_MSTR SPI_CR1_MSTR_Msk

#define	SPI_CR1_BR_Pos (3U)

#define	SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos)

#define	SPI_CR1_BR SPI_CR1_BR_Msk

#define	SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos)

#define	SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos)

#define	SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos)

#define	SPI_CR1_SPE_Pos (6U)

#define	SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)

#define	SPI_CR1_SPE SPI_CR1_SPE_Msk

#define	SPI_CR1_LSBFIRST_Pos (7U)

#define	SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos)

#define	SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk

#define	SPI_CR1_SSI_Pos (8U)

#define	SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)

#define	SPI_CR1_SSI SPI_CR1_SSI_Msk

#define	SPI_CR1_SSM_Pos (9U)

#define	SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos)

#define	SPI_CR1_SSM SPI_CR1_SSM_Msk

#define	SPI_CR1_RXONLY_Pos (10U)

#define	SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos)

#define	SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk

#define	SPI_CR1_CRCL_Pos (11U)

#define	SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos)

#define	SPI_CR1_CRCL SPI_CR1_CRCL_Msk

#define	SPI_CR1_CRCNEXT_Pos (12U)

#define	SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos)

#define	SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk

#define	SPI_CR1_CRCEN_Pos (13U)

#define	SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos)

#define	SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk

#define	SPI_CR1_BIDIOE_Pos (14U)

#define	SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos)

#define	SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk

#define	SPI_CR1_BIDIMODE_Pos (15U)

#define	SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos)

#define	SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk

#define	SPI_CR2_RXDMAEN_Pos (0U)

#define	SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos)

#define	SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk

#define	SPI_CR2_TXDMAEN_Pos (1U)

#define	SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos)

#define	SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk

#define	SPI_CR2_SSOE_Pos (2U)

#define	SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos)

#define	SPI_CR2_SSOE SPI_CR2_SSOE_Msk

#define	SPI_CR2_NSSP_Pos (3U)

#define	SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos)

#define	SPI_CR2_NSSP SPI_CR2_NSSP_Msk

#define	SPI_CR2_FRF_Pos (4U)

#define	SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos)

#define	SPI_CR2_FRF SPI_CR2_FRF_Msk

#define	SPI_CR2_ERRIE_Pos (5U)

#define	SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos)

#define	SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk

#define	SPI_CR2_RXNEIE_Pos (6U)

#define	SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos)

#define	SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk

#define	SPI_CR2_TXEIE_Pos (7U)

#define	SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos)

#define	SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk

#define	SPI_CR2_DS_Pos (8U)

#define	SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos)

#define	SPI_CR2_DS SPI_CR2_DS_Msk

#define	SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos)

#define	SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos)

#define	SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos)

#define	SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos)

#define	SPI_CR2_FRXTH_Pos (12U)

#define	SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos)

#define	SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk

#define	SPI_CR2_LDMARX_Pos (13U)

#define	SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos)

#define	SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk

#define	SPI_CR2_LDMATX_Pos (14U)

#define	SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos)

#define	SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk

#define	SPI_SR_RXNE_Pos (0U)

#define	SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos)

#define	SPI_SR_RXNE SPI_SR_RXNE_Msk

#define	SPI_SR_TXE_Pos (1U)

#define	SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos)

#define	SPI_SR_TXE SPI_SR_TXE_Msk

#define	SPI_SR_CHSIDE_Pos (2U)

#define	SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos)

#define	SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk

#define	SPI_SR_UDR_Pos (3U)

#define	SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)

#define	SPI_SR_UDR SPI_SR_UDR_Msk

#define	SPI_SR_CRCERR_Pos (4U)

#define	SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos)

#define	SPI_SR_CRCERR SPI_SR_CRCERR_Msk

#define	SPI_SR_MODF_Pos (5U)

#define	SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)

#define	SPI_SR_MODF SPI_SR_MODF_Msk

#define	SPI_SR_OVR_Pos (6U)

#define	SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)

#define	SPI_SR_OVR SPI_SR_OVR_Msk

#define	SPI_SR_BSY_Pos (7U)

#define	SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos)

#define	SPI_SR_BSY SPI_SR_BSY_Msk

#define	SPI_SR_FRE_Pos (8U)

#define	SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos)

#define	SPI_SR_FRE SPI_SR_FRE_Msk

#define	SPI_SR_FRLVL_Pos (9U)

#define	SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos)

#define	SPI_SR_FRLVL SPI_SR_FRLVL_Msk

#define	SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos)

#define	SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos)

#define	SPI_SR_FTLVL_Pos (11U)

#define	SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos)

#define	SPI_SR_FTLVL SPI_SR_FTLVL_Msk

#define	SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos)

#define	SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos)

#define	SPI_DR_DR_Pos (0U)

#define	SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos)

#define	SPI_DR_DR SPI_DR_DR_Msk

#define	SPI_CRCPR_CRCPOLY_Pos (0U)

#define	SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)

#define	SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk

#define	SPI_RXCRCR_RXCRC_Pos (0U)

#define	SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)

#define	SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk

#define	SPI_TXCRCR_TXCRC_Pos (0U)

#define	SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)

#define	SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk

#define	SPI_I2SCFGR_CHLEN_Pos (0U)

#define	SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos)

#define	SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk

#define	SPI_I2SCFGR_DATLEN_Pos (1U)

#define	SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos)

#define	SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk

#define	SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos)

#define	SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos)

#define	SPI_I2SCFGR_CKPOL_Pos (3U)

#define	SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos)

#define	SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk

#define	SPI_I2SCFGR_I2SSTD_Pos (4U)

#define	SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)

#define	SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk

#define	SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)

#define	SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)

#define	SPI_I2SCFGR_PCMSYNC_Pos (7U)

#define	SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)

#define	SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk

#define	SPI_I2SCFGR_I2SCFG_Pos (8U)

#define	SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)

#define	SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk

#define	SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)

#define	SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)

#define	SPI_I2SCFGR_I2SE_Pos (10U)

#define	SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos)

#define	SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk

#define	SPI_I2SCFGR_I2SMOD_Pos (11U)

#define	SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)

#define	SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk

#define	SPI_I2SCFGR_ASTRTEN_Pos (12U)

#define	SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)

#define	SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk

#define	SPI_I2SPR_I2SDIV_Pos (0U)

#define	SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos)

#define	SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk

#define	SPI_I2SPR_ODD_Pos (8U)

#define	SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos)

#define	SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk

#define	SPI_I2SPR_MCKOE_Pos (9U)

#define	SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos)

#define	SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk

#define	TAMP_CR1_TAMP1E_Pos (0U)

#define	TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos)

#define	TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk

#define	TAMP_CR1_TAMP2E_Pos (1U)

#define	TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos)

#define	TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk

#define	TAMP_CR1_TAMP3E_Pos (2U)

#define	TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos)

#define	TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk

#define	TAMP_CR1_ITAMP3E_Pos (18U)

#define	TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos)

#define	TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk

#define	TAMP_CR1_ITAMP5E_Pos (20U)

#define	TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos)

#define	TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk

#define	TAMP_CR1_ITAMP6E_Pos (21U)

#define	TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos)

#define	TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk

#define	TAMP_CR1_ITAMP8E_Pos (23U)

#define	TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos)

#define	TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk

#define	TAMP_CR2_TAMP1NOERASE_Pos (0U)

#define	TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos)

#define	TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk

#define	TAMP_CR2_TAMP2NOERASE_Pos (1U)

#define	TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos)

#define	TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk

#define	TAMP_CR2_TAMP3NOERASE_Pos (2U)

#define	TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos)

#define	TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk

#define	TAMP_CR2_TAMP1MSK_Pos (16U)

#define	TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos)

#define	TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk

#define	TAMP_CR2_TAMP2MSK_Pos (17U)

#define	TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos)

#define	TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk

#define	TAMP_CR2_TAMP3MSK_Pos (18U)

#define	TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos)

#define	TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk

#define	TAMP_CR2_BKERASE_Pos (23U)

#define	TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos)

#define	TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk

#define	TAMP_CR2_TAMP1TRG_Pos (24U)

#define	TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos)

#define	TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk

#define	TAMP_CR2_TAMP2TRG_Pos (25U)

#define	TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos)

#define	TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk

#define	TAMP_CR2_TAMP3TRG_Pos (26U)

#define	TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos)

#define	TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk

#define	TAMP_CR3_ITAMP3NOER_Pos (2U)

#define	TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos)

#define	TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk

#define	TAMP_CR3_ITAMP5NOER_Pos (4U)

#define	TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos)

#define	TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk

#define	TAMP_CR3_ITAMP6NOER_Pos (5U)

#define	TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos)

#define	TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk

#define	TAMP_CR3_ITAMP8NOER_Pos (7U)

#define	TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos)

#define	TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk

#define	TAMP_FLTCR_TAMPFREQ_Pos (0U)

#define	TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos)

#define	TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk

#define	TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos)

#define	TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos)

#define	TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos)

#define	TAMP_FLTCR_TAMPFLT_Pos (3U)

#define	TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos)

#define	TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk

#define	TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos)

#define	TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos)

#define	TAMP_FLTCR_TAMPPRCH_Pos (5U)

#define	TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos)

#define	TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk

#define	TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos)

#define	TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos)

#define	TAMP_FLTCR_TAMPPUDIS_Pos (7U)

#define	TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos)

#define	TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk

#define	TAMP_IER_TAMP1IE_Pos (0U)

#define	TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos)

#define	TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk

#define	TAMP_IER_TAMP2IE_Pos (1U)

#define	TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos)

#define	TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk

#define	TAMP_IER_TAMP3IE_Pos (2U)

#define	TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos)

#define	TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk

#define	TAMP_IER_ITAMP3IE_Pos (18U)

#define	TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos)

#define	TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk

#define	TAMP_IER_ITAMP5IE_Pos (20U)

#define	TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos)

#define	TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk

#define	TAMP_IER_ITAMP6IE_Pos (21U)

#define	TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos)

#define	TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk

#define	TAMP_IER_ITAMP8IE_Pos (23U)

#define	TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos)

#define	TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk

#define	TAMP_SR_TAMP1F_Pos (0U)

#define	TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos)

#define	TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk

#define	TAMP_SR_TAMP2F_Pos (1U)

#define	TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos)

#define	TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk

#define	TAMP_SR_TAMP3F_Pos (2U)

#define	TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos)

#define	TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk

#define	TAMP_SR_ITAMP3F_Pos (18U)

#define	TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos)

#define	TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk

#define	TAMP_SR_ITAMP5F_Pos (20U)

#define	TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos)

#define	TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk

#define	TAMP_SR_ITAMP6F_Pos (21U)

#define	TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos)

#define	TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk

#define	TAMP_SR_ITAMP8F_Pos (23U)

#define	TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos)

#define	TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk

#define	TAMP_MISR_TAMP1MF_Pos (0U)

#define	TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos)

#define	TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk

#define	TAMP_MISR_TAMP2MF_Pos (1U)

#define	TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos)

#define	TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk

#define	TAMP_MISR_TAMP3MF_Pos (2U)

#define	TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos)

#define	TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk

#define	TAMP_MISR_ITAMP3MF_Pos (18U)

#define	TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos)

#define	TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk

#define	TAMP_MISR_ITAMP5MF_Pos (20U)

#define	TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos)

#define	TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk

#define	TAMP_MISR_ITAMP6MF_Pos (21U)

#define	TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos)

#define	TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk

#define	TAMP_MISR_ITAMP8MF_Pos (23U)

#define	TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos)

#define	TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk

#define	TAMP_SMISR_TAMP1MF_Pos (0U)

#define	TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos)

#define	TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk

#define	TAMP_SMISR_TAMP2MF_Pos (1U)

#define	TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos)

#define	TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk

#define	TAMP_SMISR_TAMP3MF_Pos (2U)

#define	TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos)

#define	TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk

#define	TAMP_SMISR_ITAMP3MF_Pos (18U)

#define	TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos)

#define	TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk

#define	TAMP_SMISR_ITAMP5MF_Pos (20U)

#define	TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos)

#define	TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk

#define	TAMP_SMISR_ITAMP6MF_Pos (21U)

#define	TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos)

#define	TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk

#define	TAMP_SMISR_ITAMP8MF_Pos (23U)

#define	TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos)

#define	TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk

#define	TAMP_SCR_CTAMP1F_Pos (0U)

#define	TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos)

#define	TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk

#define	TAMP_SCR_CTAMP2F_Pos (1U)

#define	TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos)

#define	TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk

#define	TAMP_SCR_CTAMP3F_Pos (2U)

#define	TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos)

#define	TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk

#define	TAMP_SCR_CITAMP3F_Pos (18U)

#define	TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos)

#define	TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk

#define	TAMP_SCR_CITAMP5F_Pos (20U)

#define	TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos)

#define	TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk

#define	TAMP_SCR_CITAMP6F_Pos (21U)

#define	TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos)

#define	TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk

#define	TAMP_SCR_CITAMP8F_Pos (23U)

#define	TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos)

#define	TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk

#define	TAMP_COUNTR_Pos (0U)

#define	TAMP_COUNTR_Msk (0xFFFFFFFFUL << TAMP_COUNTR_Pos)

#define	TAMP_COUNTR TAMP_COUNTR_Msk

#define	TAMP_BKP0R_Pos (0U)

#define	TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos)

#define	TAMP_BKP0R TAMP_BKP0R_Msk

#define	TAMP_BKP1R_Pos (0U)

#define	TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos)

#define	TAMP_BKP1R TAMP_BKP1R_Msk

#define	TAMP_BKP2R_Pos (0U)

#define	TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos)

#define	TAMP_BKP2R TAMP_BKP2R_Msk

#define	TAMP_BKP3R_Pos (0U)

#define	TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos)

#define	TAMP_BKP3R TAMP_BKP3R_Msk

#define	TAMP_BKP4R_Pos (0U)

#define	TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos)

#define	TAMP_BKP4R TAMP_BKP4R_Msk

#define	TAMP_BKP5R_Pos (0U)

#define	TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos)

#define	TAMP_BKP5R TAMP_BKP5R_Msk

#define	TAMP_BKP6R_Pos (0U)

#define	TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos)

#define	TAMP_BKP6R TAMP_BKP6R_Msk

#define	TAMP_BKP7R_Pos (0U)

#define	TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos)

#define	TAMP_BKP7R TAMP_BKP7R_Msk

#define	TAMP_BKP8R_Pos (0U)

#define	TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos)

#define	TAMP_BKP8R TAMP_BKP8R_Msk

#define	TAMP_BKP9R_Pos (0U)

#define	TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos)

#define	TAMP_BKP9R TAMP_BKP9R_Msk

#define	TAMP_BKP10R_Pos (0U)

#define	TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos)

#define	TAMP_BKP10R TAMP_BKP10R_Msk

#define	TAMP_BKP11R_Pos (0U)

#define	TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos)

#define	TAMP_BKP11R TAMP_BKP11R_Msk

#define	TAMP_BKP12R_Pos (0U)

#define	TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos)

#define	TAMP_BKP12R TAMP_BKP12R_Msk

#define	TAMP_BKP13R_Pos (0U)

#define	TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos)

#define	TAMP_BKP13R TAMP_BKP13R_Msk

#define	TAMP_BKP14R_Pos (0U)

#define	TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos)

#define	TAMP_BKP14R TAMP_BKP14R_Msk

#define	TAMP_BKP15R_Pos (0U)

#define	TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos)

#define	TAMP_BKP15R TAMP_BKP15R_Msk

#define	TAMP_BKP16R_Pos (0U)

#define	TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos)

#define	TAMP_BKP16R TAMP_BKP16R_Msk

#define	TAMP_BKP17R_Pos (0U)

#define	TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos)

#define	TAMP_BKP17R TAMP_BKP17R_Msk

#define	TAMP_BKP18R_Pos (0U)

#define	TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos)

#define	TAMP_BKP18R TAMP_BKP18R_Msk

#define	TAMP_BKP19R_Pos (0U)

#define	TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos)

#define	TAMP_BKP19R TAMP_BKP19R_Msk

#define	SYSCFG_MEMRMP_MEM_MODE_Pos (0U)

#define	SYSCFG_MEMRMP_MEM_MODE_Msk (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos)

#define	SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk

#define	SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)

#define	SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)

#define	SYSCFG_MEMRMP_MEM_MODE_2 (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos)

#define	SYSCFG_CFGR1_BOOSTEN_Pos (8U)

#define	SYSCFG_CFGR1_BOOSTEN_Msk (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos)

#define	SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk

#define	SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)

#define	SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos)

#define	SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk

#define	SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)

#define	SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos)

#define	SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk

#define	SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U)

#define	SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos)

#define	SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk

#define	SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U)

#define	SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos)

#define	SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk

#define	SYSCFG_CFGR1_I2C1_FMP_Pos (20U)

#define	SYSCFG_CFGR1_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos)

#define	SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk

#define	SYSCFG_CFGR1_I2C2_FMP_Pos (21U)

#define	SYSCFG_CFGR1_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos)

#define	SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk

#define	SYSCFG_CFGR1_I2C3_FMP_Pos (22U)

#define	SYSCFG_CFGR1_I2C3_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C3_FMP_Pos)

#define	SYSCFG_CFGR1_I2C3_FMP SYSCFG_CFGR1_I2C3_FMP_Msk

#define	SYSCFG_EXTICR1_EXTI0_Pos (0U)

#define	SYSCFG_EXTICR1_EXTI0_Msk (0x7UL << SYSCFG_EXTICR1_EXTI0_Pos)

#define	SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk

#define	SYSCFG_EXTICR1_EXTI1_Pos (4U)

#define	SYSCFG_EXTICR1_EXTI1_Msk (0x7UL << SYSCFG_EXTICR1_EXTI1_Pos)

#define	SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk

#define	SYSCFG_EXTICR1_EXTI2_Pos (8U)

#define	SYSCFG_EXTICR1_EXTI2_Msk (0x7UL << SYSCFG_EXTICR1_EXTI2_Pos)

#define	SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk

#define	SYSCFG_EXTICR1_EXTI3_Pos (12U)

#define	SYSCFG_EXTICR1_EXTI3_Msk (0x7UL << SYSCFG_EXTICR1_EXTI3_Pos)

#define	SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk

#define	SYSCFG_EXTICR1_EXTI0_PA (0x00000000U)
	External Interrupt Line 0 Source Input configuration.

#define	SYSCFG_EXTICR1_EXTI0_PB (0x00000001U)

#define	SYSCFG_EXTICR1_EXTI0_PC (0x00000002U)

#define	SYSCFG_EXTICR1_EXTI1_PA (0x00000000U)
	External Interrupt Line 1 Source Input configuration.

#define	SYSCFG_EXTICR1_EXTI1_PB (0x00000010U)

#define	SYSCFG_EXTICR1_EXTI1_PC (0x00000020U)

#define	SYSCFG_EXTICR1_EXTI2_PA (0x00000000U)
	External Interrupt Line 2 Source Input configuration.

#define	SYSCFG_EXTICR1_EXTI2_PB (0x00000100U)

#define	SYSCFG_EXTICR1_EXTI2_PC (0x00000200U)

#define	SYSCFG_EXTICR1_EXTI3_PA (0x00000000U)
	External Interrupt Line 3 Source Input configuration.

#define	SYSCFG_EXTICR1_EXTI3_PB (0x00001000U)

#define	SYSCFG_EXTICR1_EXTI3_PC (0x00002000U)

#define	SYSCFG_EXTICR2_EXTI4_Pos (0U)

#define	SYSCFG_EXTICR2_EXTI4_Msk (0x7UL << SYSCFG_EXTICR2_EXTI4_Pos)

#define	SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk

#define	SYSCFG_EXTICR2_EXTI5_Pos (4U)

#define	SYSCFG_EXTICR2_EXTI5_Msk (0x7UL << SYSCFG_EXTICR2_EXTI5_Pos)

#define	SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk

#define	SYSCFG_EXTICR2_EXTI6_Pos (8U)

#define	SYSCFG_EXTICR2_EXTI6_Msk (0x7UL << SYSCFG_EXTICR2_EXTI6_Pos)

#define	SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk

#define	SYSCFG_EXTICR2_EXTI7_Pos (12U)

#define	SYSCFG_EXTICR2_EXTI7_Msk (0x7UL << SYSCFG_EXTICR2_EXTI7_Pos)

#define	SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk

#define	SYSCFG_EXTICR2_EXTI4_PA (0x00000000U)
	External Interrupt Line 4 Source Input configuration.

#define	SYSCFG_EXTICR2_EXTI4_PB (0x00000001U)

#define	SYSCFG_EXTICR2_EXTI4_PC (0x00000002U)

#define	SYSCFG_EXTICR2_EXTI5_PA (0x00000000U)
	External Interrupt Line 5 Source Input configuration.

#define	SYSCFG_EXTICR2_EXTI5_PB (0x00000010U)

#define	SYSCFG_EXTICR2_EXTI5_PC (0x00000020U)

#define	SYSCFG_EXTICR2_EXTI6_PA (0x00000000U)
	External Interrupt Line 6 Source Input configuration.

#define	SYSCFG_EXTICR2_EXTI6_PB (0x00000100U)

#define	SYSCFG_EXTICR2_EXTI6_PC (0x00000200U)

#define	SYSCFG_EXTICR2_EXTI7_PA (0x00000000U)
	External Interrupt Line 7 Source Input configuration.

#define	SYSCFG_EXTICR2_EXTI7_PB (0x00001000U)

#define	SYSCFG_EXTICR3_EXTI8_Pos (0U)

#define	SYSCFG_EXTICR3_EXTI8_Msk (0x7UL << SYSCFG_EXTICR3_EXTI8_Pos)

#define	SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk

#define	SYSCFG_EXTICR3_EXTI9_Pos (4U)

#define	SYSCFG_EXTICR3_EXTI9_Msk (0x7UL << SYSCFG_EXTICR3_EXTI9_Pos)

#define	SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk

#define	SYSCFG_EXTICR3_EXTI10_Pos (8U)

#define	SYSCFG_EXTICR3_EXTI10_Msk (0x7UL << SYSCFG_EXTICR3_EXTI10_Pos)

#define	SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk

#define	SYSCFG_EXTICR3_EXTI11_Pos (12U)

#define	SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)

#define	SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk

#define	SYSCFG_EXTICR3_EXTI8_PA (0x00000000U)
	External Interrupt Line 8 Source Input configuration.

#define	SYSCFG_EXTICR3_EXTI8_PB (0x00000001U)

#define	SYSCFG_EXTICR3_EXTI9_PA (0x00000000U)
	External Interrupt Line 9 Source Input configuration.

#define	SYSCFG_EXTICR3_EXTI9_PB (0x00000010U)

#define	SYSCFG_EXTICR3_EXTI10_PA (0x00000000U)
	External Interrupt Line 10 Source Input configuration.

#define	SYSCFG_EXTICR3_EXTI10_PB (0x00000100U)

#define	SYSCFG_EXTICR3_EXTI11_PA (0x00000000U)
	External Interrupt Line 11 Source Input configuration.

#define	SYSCFG_EXTICR3_EXTI11_PB (0x00001000U)

#define	SYSCFG_EXTICR4_EXTI12_Pos (0U)

#define	SYSCFG_EXTICR4_EXTI12_Msk (0x7UL << SYSCFG_EXTICR4_EXTI12_Pos)

#define	SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk

#define	SYSCFG_EXTICR4_EXTI13_Pos (4U)

#define	SYSCFG_EXTICR4_EXTI13_Msk (0x7UL << SYSCFG_EXTICR4_EXTI13_Pos)

#define	SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk

#define	SYSCFG_EXTICR4_EXTI14_Pos (8U)

#define	SYSCFG_EXTICR4_EXTI14_Msk (0x7UL << SYSCFG_EXTICR4_EXTI14_Pos)

#define	SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk

#define	SYSCFG_EXTICR4_EXTI15_Pos (12U)

#define	SYSCFG_EXTICR4_EXTI15_Msk (0x7UL << SYSCFG_EXTICR4_EXTI15_Pos)

#define	SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk

#define	SYSCFG_EXTICR4_EXTI12_PA (0x00000000U)
	External Interrupt Line 12 Source Input configuration.

#define	SYSCFG_EXTICR4_EXTI12_PB (0x00000001U)

#define	SYSCFG_EXTICR4_EXTI13_PA (0x00000000U)
	External Interrupt Line 13 Source Input configuration.

#define	SYSCFG_EXTICR4_EXTI13_PB (0x00000010U)

#define	SYSCFG_EXTICR4_EXTI13_PC (0x00000020U)

#define	SYSCFG_EXTICR4_EXTI14_PA (0x00000000U)
	External Interrupt Line 14 Source Input configuration.

#define	SYSCFG_EXTICR4_EXTI14_PB (0x00000100U)

#define	SYSCFG_EXTICR4_EXTI14_PC (0x00000200U)

#define	SYSCFG_EXTICR4_EXTI15_PA (0x00000000U)
	External Interrupt Line 15 Source Input configuration.

#define	SYSCFG_EXTICR4_EXTI15_PB (0x00001000U)

#define	SYSCFG_EXTICR4_EXTI15_PC (0x00002000U)

#define	SYSCFG_SCSR_SRAM2ER_Pos (0U)

#define	SYSCFG_SCSR_SRAM2ER_Msk (0x1UL << SYSCFG_SCSR_SRAM2ER_Pos)

#define	SYSCFG_SCSR_SRAM2ER SYSCFG_SCSR_SRAM2ER_Msk

#define	SYSCFG_SCSR_SRAMBSY_Pos (1U)

#define	SYSCFG_SCSR_SRAMBSY_Msk (0x1UL << SYSCFG_SCSR_SRAMBSY_Pos)

#define	SYSCFG_SCSR_SRAMBSY SYSCFG_SCSR_SRAMBSY_Msk

#define	SYSCFG_SCSR_PKASRAMBSY_Pos (8U)

#define	SYSCFG_SCSR_PKASRAMBSY_Msk (0x1UL << SYSCFG_SCSR_PKASRAMBSY_Pos)

#define	SYSCFG_SCSR_PKASRAMBSY SYSCFG_SCSR_PKASRAMBSY_Msk

#define	SYSCFG_CFGR2_CLL_Pos (0U)

#define	SYSCFG_CFGR2_CLL_Msk (0x1UL << SYSCFG_CFGR2_CLL_Pos)

#define	SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk

#define	SYSCFG_CFGR2_SPL_Pos (1U)

#define	SYSCFG_CFGR2_SPL_Msk (0x1UL << SYSCFG_CFGR2_SPL_Pos)

#define	SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk

#define	SYSCFG_CFGR2_PVDL_Pos (2U)

#define	SYSCFG_CFGR2_PVDL_Msk (0x1UL << SYSCFG_CFGR2_PVDL_Pos)

#define	SYSCFG_CFGR2_PVDL SYSCFG_CFGR2_PVDL_Msk

#define	SYSCFG_CFGR2_ECCL_Pos (3U)

#define	SYSCFG_CFGR2_ECCL_Msk (0x1UL << SYSCFG_CFGR2_ECCL_Pos)

#define	SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk

#define	SYSCFG_CFGR2_SPF_Pos (8U)

#define	SYSCFG_CFGR2_SPF_Msk (0x1UL << SYSCFG_CFGR2_SPF_Pos)

#define	SYSCFG_CFGR2_SPF SYSCFG_CFGR2_SPF_Msk

#define	SYSCFG_SWPR_PAGE0_Pos (0U)

#define	SYSCFG_SWPR_PAGE0_Msk (0x1UL << SYSCFG_SWPR_PAGE0_Pos)

#define	SYSCFG_SWPR_PAGE0 SYSCFG_SWPR_PAGE0_Msk

#define	SYSCFG_SWPR_PAGE1_Pos (1U)

#define	SYSCFG_SWPR_PAGE1_Msk (0x1UL << SYSCFG_SWPR_PAGE1_Pos)

#define	SYSCFG_SWPR_PAGE1 SYSCFG_SWPR_PAGE1_Msk

#define	SYSCFG_SWPR_PAGE2_Pos (2U)

#define	SYSCFG_SWPR_PAGE2_Msk (0x1UL << SYSCFG_SWPR_PAGE2_Pos)

#define	SYSCFG_SWPR_PAGE2 SYSCFG_SWPR_PAGE2_Msk

#define	SYSCFG_SWPR_PAGE3_Pos (3U)

#define	SYSCFG_SWPR_PAGE3_Msk (0x1UL << SYSCFG_SWPR_PAGE3_Pos)

#define	SYSCFG_SWPR_PAGE3 SYSCFG_SWPR_PAGE3_Msk

#define	SYSCFG_SWPR_PAGE4_Pos (4U)

#define	SYSCFG_SWPR_PAGE4_Msk (0x1UL << SYSCFG_SWPR_PAGE4_Pos)

#define	SYSCFG_SWPR_PAGE4 SYSCFG_SWPR_PAGE4_Msk

#define	SYSCFG_SWPR_PAGE5_Pos (5U)

#define	SYSCFG_SWPR_PAGE5_Msk (0x1UL << SYSCFG_SWPR_PAGE5_Pos)

#define	SYSCFG_SWPR_PAGE5 SYSCFG_SWPR_PAGE5_Msk

#define	SYSCFG_SWPR_PAGE6_Pos (6U)

#define	SYSCFG_SWPR_PAGE6_Msk (0x1UL << SYSCFG_SWPR_PAGE6_Pos)

#define	SYSCFG_SWPR_PAGE6 SYSCFG_SWPR_PAGE6_Msk

#define	SYSCFG_SWPR_PAGE7_Pos (7U)

#define	SYSCFG_SWPR_PAGE7_Msk (0x1UL << SYSCFG_SWPR_PAGE7_Pos)

#define	SYSCFG_SWPR_PAGE7 SYSCFG_SWPR_PAGE7_Msk

#define	SYSCFG_SWPR_PAGE8_Pos (8U)

#define	SYSCFG_SWPR_PAGE8_Msk (0x1UL << SYSCFG_SWPR_PAGE8_Pos)

#define	SYSCFG_SWPR_PAGE8 SYSCFG_SWPR_PAGE8_Msk

#define	SYSCFG_SWPR_PAGE9_Pos (9U)

#define	SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos)

#define	SYSCFG_SWPR_PAGE9 SYSCFG_SWPR_PAGE9_Msk

#define	SYSCFG_SWPR_PAGE10_Pos (10U)

#define	SYSCFG_SWPR_PAGE10_Msk (0x1UL << SYSCFG_SWPR_PAGE10_Pos)

#define	SYSCFG_SWPR_PAGE10 SYSCFG_SWPR_PAGE10_Msk

#define	SYSCFG_SWPR_PAGE11_Pos (11U)

#define	SYSCFG_SWPR_PAGE11_Msk (0x1UL << SYSCFG_SWPR_PAGE11_Pos)

#define	SYSCFG_SWPR_PAGE11 SYSCFG_SWPR_PAGE11_Msk

#define	SYSCFG_SWPR_PAGE12_Pos (12U)

#define	SYSCFG_SWPR_PAGE12_Msk (0x1UL << SYSCFG_SWPR_PAGE12_Pos)

#define	SYSCFG_SWPR_PAGE12 SYSCFG_SWPR_PAGE12_Msk

#define	SYSCFG_SWPR_PAGE13_Pos (13U)

#define	SYSCFG_SWPR_PAGE13_Msk (0x1UL << SYSCFG_SWPR_PAGE13_Pos)

#define	SYSCFG_SWPR_PAGE13 SYSCFG_SWPR_PAGE13_Msk

#define	SYSCFG_SWPR_PAGE14_Pos (14U)

#define	SYSCFG_SWPR_PAGE14_Msk (0x1UL << SYSCFG_SWPR_PAGE14_Pos)

#define	SYSCFG_SWPR_PAGE14 SYSCFG_SWPR_PAGE14_Msk

#define	SYSCFG_SWPR_PAGE15_Pos (15U)

#define	SYSCFG_SWPR_PAGE15_Msk (0x1UL << SYSCFG_SWPR_PAGE15_Pos)

#define	SYSCFG_SWPR_PAGE15 SYSCFG_SWPR_PAGE15_Msk

#define	SYSCFG_SWPR_PAGE16_Pos (16U)

#define	SYSCFG_SWPR_PAGE16_Msk (0x1UL << SYSCFG_SWPR_PAGE16_Pos)

#define	SYSCFG_SWPR_PAGE16 SYSCFG_SWPR_PAGE16_Msk

#define	SYSCFG_SWPR_PAGE17_Pos (17U)

#define	SYSCFG_SWPR_PAGE17_Msk (0x1UL << SYSCFG_SWPR_PAGE17_Pos)

#define	SYSCFG_SWPR_PAGE17 SYSCFG_SWPR_PAGE17_Msk

#define	SYSCFG_SWPR_PAGE18_Pos (18U)

#define	SYSCFG_SWPR_PAGE18_Msk (0x1UL << SYSCFG_SWPR_PAGE18_Pos)

#define	SYSCFG_SWPR_PAGE18 SYSCFG_SWPR_PAGE18_Msk

#define	SYSCFG_SWPR_PAGE19_Pos (19U)

#define	SYSCFG_SWPR_PAGE19_Msk (0x1UL << SYSCFG_SWPR_PAGE19_Pos)

#define	SYSCFG_SWPR_PAGE19 SYSCFG_SWPR_PAGE19_Msk

#define	SYSCFG_SWPR_PAGE20_Pos (20U)

#define	SYSCFG_SWPR_PAGE20_Msk (0x1UL << SYSCFG_SWPR_PAGE20_Pos)

#define	SYSCFG_SWPR_PAGE20 SYSCFG_SWPR_PAGE20_Msk

#define	SYSCFG_SWPR_PAGE21_Pos (21U)

#define	SYSCFG_SWPR_PAGE21_Msk (0x1UL << SYSCFG_SWPR_PAGE21_Pos)

#define	SYSCFG_SWPR_PAGE21 SYSCFG_SWPR_PAGE21_Msk

#define	SYSCFG_SWPR_PAGE22_Pos (22U)

#define	SYSCFG_SWPR_PAGE22_Msk (0x1UL << SYSCFG_SWPR_PAGE22_Pos)

#define	SYSCFG_SWPR_PAGE22 SYSCFG_SWPR_PAGE22_Msk

#define	SYSCFG_SWPR_PAGE23_Pos (23U)

#define	SYSCFG_SWPR_PAGE23_Msk (0x1UL << SYSCFG_SWPR_PAGE23_Pos)

#define	SYSCFG_SWPR_PAGE23 SYSCFG_SWPR_PAGE23_Msk

#define	SYSCFG_SWPR_PAGE24_Pos (24U)

#define	SYSCFG_SWPR_PAGE24_Msk (0x1UL << SYSCFG_SWPR_PAGE24_Pos)

#define	SYSCFG_SWPR_PAGE24 SYSCFG_SWPR_PAGE24_Msk

#define	SYSCFG_SWPR_PAGE25_Pos (25U)

#define	SYSCFG_SWPR_PAGE25_Msk (0x1UL << SYSCFG_SWPR_PAGE25_Pos)

#define	SYSCFG_SWPR_PAGE25 SYSCFG_SWPR_PAGE25_Msk

#define	SYSCFG_SWPR_PAGE26_Pos (26U)

#define	SYSCFG_SWPR_PAGE26_Msk (0x1UL << SYSCFG_SWPR_PAGE26_Pos)

#define	SYSCFG_SWPR_PAGE26 SYSCFG_SWPR_PAGE26_Msk

#define	SYSCFG_SWPR_PAGE27_Pos (27U)

#define	SYSCFG_SWPR_PAGE27_Msk (0x1UL << SYSCFG_SWPR_PAGE27_Pos)

#define	SYSCFG_SWPR_PAGE27 SYSCFG_SWPR_PAGE27_Msk

#define	SYSCFG_SWPR_PAGE28_Pos (28U)

#define	SYSCFG_SWPR_PAGE28_Msk (0x1UL << SYSCFG_SWPR_PAGE28_Pos)

#define	SYSCFG_SWPR_PAGE28 SYSCFG_SWPR_PAGE28_Msk

#define	SYSCFG_SWPR_PAGE29_Pos (29U)

#define	SYSCFG_SWPR_PAGE29_Msk (0x1UL << SYSCFG_SWPR_PAGE29_Pos)

#define	SYSCFG_SWPR_PAGE29 SYSCFG_SWPR_PAGE29_Msk

#define	SYSCFG_SWPR_PAGE30_Pos (30U)

#define	SYSCFG_SWPR_PAGE30_Msk (0x1UL << SYSCFG_SWPR_PAGE30_Pos)

#define	SYSCFG_SWPR_PAGE30 SYSCFG_SWPR_PAGE30_Msk

#define	SYSCFG_SWPR_PAGE31_Pos (31U)

#define	SYSCFG_SWPR_PAGE31_Msk (0x1UL << SYSCFG_SWPR_PAGE31_Pos)

#define	SYSCFG_SWPR_PAGE31 SYSCFG_SWPR_PAGE31_Msk

#define	SYSCFG_SKR_KEY_Pos (0U)

#define	SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos)

#define	SYSCFG_SKR_KEY SYSCFG_SKR_KEY_Msk

#define	SYSCFG_IMR1_RTCSTAMPTAMPLSECSSIM_Pos (0U)

#define	SYSCFG_IMR1_RTCSTAMPTAMPLSECSSIM_Msk (0x1UL << SYSCFG_IMR1_RTCSTAMPTAMPLSECSSIM_Pos)

#define	SYSCFG_IMR1_RTCSTAMPTAMPLSECSSIM SYSCFG_IMR1_RTCSTAMPTAMPLSECSSIM_Msk

#define	SYSCFG_IMR1_RTCSSRUIM_Pos (2U)

#define	SYSCFG_IMR1_RTCSSRUIM_Msk (0x1UL << SYSCFG_IMR1_RTCSSRUIM_Pos)

#define	SYSCFG_IMR1_RTCSSRUIM SYSCFG_IMR1_RTCSSRUIM_Msk

#define	SYSCFG_IMR1_EXTI5IM_Pos (21U)

#define	SYSCFG_IMR1_EXTI5IM_Msk (0x1UL << SYSCFG_IMR1_EXTI5IM_Pos)

#define	SYSCFG_IMR1_EXTI5IM SYSCFG_IMR1_EXTI5IM_Msk

#define	SYSCFG_IMR1_EXTI6IM_Pos (22U)

#define	SYSCFG_IMR1_EXTI6IM_Msk (0x1UL << SYSCFG_IMR1_EXTI6IM_Pos)

#define	SYSCFG_IMR1_EXTI6IM SYSCFG_IMR1_EXTI6IM_Msk

#define	SYSCFG_IMR1_EXTI7IM_Pos (23U)

#define	SYSCFG_IMR1_EXTI7IM_Msk (0x1UL << SYSCFG_IMR1_EXTI7IM_Pos)

#define	SYSCFG_IMR1_EXTI7IM SYSCFG_IMR1_EXTI7IM_Msk

#define	SYSCFG_IMR1_EXTI8IM_Pos (24U)

#define	SYSCFG_IMR1_EXTI8IM_Msk (0x1UL << SYSCFG_IMR1_EXTI8IM_Pos)

#define	SYSCFG_IMR1_EXTI8IM SYSCFG_IMR1_EXTI8IM_Msk

#define	SYSCFG_IMR1_EXTI9IM_Pos (25U)

#define	SYSCFG_IMR1_EXTI9IM_Msk (0x1UL << SYSCFG_IMR1_EXTI9IM_Pos)

#define	SYSCFG_IMR1_EXTI9IM SYSCFG_IMR1_EXTI9IM_Msk

#define	SYSCFG_IMR1_EXTI10IM_Pos (26U)

#define	SYSCFG_IMR1_EXTI10IM_Msk (0x1UL << SYSCFG_IMR1_EXTI10IM_Pos)

#define	SYSCFG_IMR1_EXTI10IM SYSCFG_IMR1_EXTI10IM_Msk

#define	SYSCFG_IMR1_EXTI11IM_Pos (27U)

#define	SYSCFG_IMR1_EXTI11IM_Msk (0x1UL << SYSCFG_IMR1_EXTI11IM_Pos)

#define	SYSCFG_IMR1_EXTI11IM SYSCFG_IMR1_EXTI11IM_Msk

#define	SYSCFG_IMR1_EXTI12IM_Pos (28U)

#define	SYSCFG_IMR1_EXTI12IM_Msk (0x1UL << SYSCFG_IMR1_EXTI12IM_Pos)

#define	SYSCFG_IMR1_EXTI12IM SYSCFG_IMR1_EXTI12IM_Msk

#define	SYSCFG_IMR1_EXTI13IM_Pos (29U)

#define	SYSCFG_IMR1_EXTI13IM_Msk (0x1UL << SYSCFG_IMR1_EXTI13IM_Pos)

#define	SYSCFG_IMR1_EXTI13IM SYSCFG_IMR1_EXTI13IM_Msk

#define	SYSCFG_IMR1_EXTI14IM_Pos (30U)

#define	SYSCFG_IMR1_EXTI14IM_Msk (0x1UL << SYSCFG_IMR1_EXTI14IM_Pos)

#define	SYSCFG_IMR1_EXTI14IM SYSCFG_IMR1_EXTI14IM_Msk

#define	SYSCFG_IMR1_EXTI15IM_Pos (31U)

#define	SYSCFG_IMR1_EXTI15IM_Msk (0x1UL << SYSCFG_IMR1_EXTI15IM_Pos)

#define	SYSCFG_IMR1_EXTI15IM SYSCFG_IMR1_EXTI15IM_Msk

#define	SYSCFG_IMR2_PVM3IM_Pos (18U)

#define	SYSCFG_IMR2_PVM3IM_Msk (0x1UL << SYSCFG_IMR2_PVM3IM_Pos)

#define	SYSCFG_IMR2_PVM3IM SYSCFG_IMR2_PVM3IM_Msk

#define	SYSCFG_IMR2_PVDIM_Pos (20U)

#define	SYSCFG_IMR2_PVDIM_Msk (0x1UL << SYSCFG_IMR2_PVDIM_Pos)

#define	SYSCFG_IMR2_PVDIM SYSCFG_IMR2_PVDIM_Msk

#define	SYSCFG_C2IMR1_RTCSTAMPTAMPLSECSSIM_Pos (0U)

#define	SYSCFG_C2IMR1_RTCSTAMPTAMPLSECSSIM_Msk (0x1U << SYSCFG_C2IMR1_RTCSTAMPTAMPLSECSSIM_Pos

#define	SYSCFG_C2IMR1_RTCSTAMPTAMPLSECSSIM SYSCFG_C2IMR1_RTCSTAMPTAMPLSECSSIM_Msk /* !< Enabling of interrupt from RTC TimeStamp, RTC Tampers and LSE Clock Security System to CPU2 */

#define	SYSCFG_C2IMR1_RTCALARMIM_Pos (1U)

#define	SYSCFG_C2IMR1_RTCALARMIM_Msk (0x1UL << SYSCFG_C2IMR1_RTCALARMIM_Pos)

#define	SYSCFG_C2IMR1_RTCALARMIM SYSCFG_C2IMR1_RTCALARMIM_Msk

#define	SYSCFG_C2IMR1_RTCSSRUIM_Pos (2U)

#define	SYSCFG_C2IMR1_RTCSSRUIM_Msk (0x1UL << SYSCFG_C2IMR1_RTCSSRUIM_Pos)

#define	SYSCFG_C2IMR1_RTCSSRUIM SYSCFG_C2IMR1_RTCSSRUIM_Msk

#define	SYSCFG_C2IMR1_RTCWKUPIM_Pos (3U)

#define	SYSCFG_C2IMR1_RTCWKUPIM_Msk (0x1UL << SYSCFG_C2IMR1_RTCWKUPIM_Pos)

#define	SYSCFG_C2IMR1_RTCWKUPIM SYSCFG_C2IMR1_RTCWKUPIM_Msk

#define	SYSCFG_C2IMR1_RCCIM_Pos (5U)

#define	SYSCFG_C2IMR1_RCCIM_Msk (0x1UL << SYSCFG_C2IMR1_RCCIM_Pos)

#define	SYSCFG_C2IMR1_RCCIM SYSCFG_C2IMR1_RCCIM_Msk

#define	SYSCFG_C2IMR1_FLASHIM_Pos (6U)

#define	SYSCFG_C2IMR1_FLASHIM_Msk (0x1UL << SYSCFG_C2IMR1_FLASHIM_Pos)

#define	SYSCFG_C2IMR1_FLASHIM SYSCFG_C2IMR1_FLASHIM_Msk

#define	SYSCFG_C2IMR1_PKAIM_Pos (8U)

#define	SYSCFG_C2IMR1_PKAIM_Msk (0x1UL << SYSCFG_C2IMR1_PKAIM_Pos)

#define	SYSCFG_C2IMR1_PKAIM SYSCFG_C2IMR1_PKAIM_Msk

#define	SYSCFG_C2IMR1_AESIM_Pos (10U)

#define	SYSCFG_C2IMR1_AESIM_Msk (0x1UL << SYSCFG_C2IMR1_AESIM_Pos)

#define	SYSCFG_C2IMR1_AESIM SYSCFG_C2IMR1_AESIM_Msk

#define	SYSCFG_C2IMR1_COMPIM_Pos (11U)

#define	SYSCFG_C2IMR1_COMPIM_Msk (0x1UL << SYSCFG_C2IMR1_COMPIM_Pos)

#define	SYSCFG_C2IMR1_COMPIM SYSCFG_C2IMR1_COMPIM_Msk

#define	SYSCFG_C2IMR1_ADCIM_Pos (12U)

#define	SYSCFG_C2IMR1_ADCIM_Msk (0x1UL << SYSCFG_C2IMR1_ADCIM_Pos)

#define	SYSCFG_C2IMR1_ADCIM SYSCFG_C2IMR1_ADCIM_Msk

#define	SYSCFG_C2IMR1_DACIM_Pos (13U)

#define	SYSCFG_C2IMR1_DACIM_Msk (0x1UL << SYSCFG_C2IMR1_DACIM_Pos)

#define	SYSCFG_C2IMR1_DACIM SYSCFG_C2IMR1_DACIM_Msk

#define	SYSCFG_C2IMR1_EXTI0IM_Pos (16U)

#define	SYSCFG_C2IMR1_EXTI0IM_Msk (0x1UL << SYSCFG_C2IMR1_EXTI0IM_Pos)

#define	SYSCFG_C2IMR1_EXTI0IM SYSCFG_C2IMR1_EXTI0IM_Msk

#define	SYSCFG_C2IMR1_EXTI1IM_Pos (17U)

#define	SYSCFG_C2IMR1_EXTI1IM_Msk (0x1UL << SYSCFG_C2IMR1_EXTI1IM_Pos)

#define	SYSCFG_C2IMR1_EXTI1IM SYSCFG_C2IMR1_EXTI1IM_Msk

#define	SYSCFG_C2IMR1_EXTI2IM_Pos (18U)

#define	SYSCFG_C2IMR1_EXTI2IM_Msk (0x1UL << SYSCFG_C2IMR1_EXTI2IM_Pos)

#define	SYSCFG_C2IMR1_EXTI2IM SYSCFG_C2IMR1_EXTI2IM_Msk

#define	SYSCFG_C2IMR1_EXTI3IM_Pos (19U)

#define	SYSCFG_C2IMR1_EXTI3IM_Msk (0x1UL << SYSCFG_C2IMR1_EXTI3IM_Pos)

#define	SYSCFG_C2IMR1_EXTI3IM SYSCFG_C2IMR1_EXTI3IM_Msk

#define	SYSCFG_C2IMR1_EXTI4IM_Pos (20U)

#define	SYSCFG_C2IMR1_EXTI4IM_Msk (0x1UL << SYSCFG_C2IMR1_EXTI4IM_Pos)

#define	SYSCFG_C2IMR1_EXTI4IM SYSCFG_C2IMR1_EXTI4IM_Msk

#define	SYSCFG_C2IMR1_EXTI5IM_Pos (21U)

#define	SYSCFG_C2IMR1_EXTI5IM_Msk (0x1UL << SYSCFG_C2IMR1_EXTI5IM_Pos)

#define	SYSCFG_C2IMR1_EXTI5IM SYSCFG_C2IMR1_EXTI5IM_Msk

#define	SYSCFG_C2IMR1_EXTI6IM_Pos (22U)

#define	SYSCFG_C2IMR1_EXTI6IM_Msk (0x1UL << SYSCFG_C2IMR1_EXTI6IM_Pos)

#define	SYSCFG_C2IMR1_EXTI6IM SYSCFG_C2IMR1_EXTI6IM_Msk

#define	SYSCFG_C2IMR1_EXTI7IM_Pos (23U)

#define	SYSCFG_C2IMR1_EXTI7IM_Msk (0x1UL << SYSCFG_C2IMR1_EXTI7IM_Pos)

#define	SYSCFG_C2IMR1_EXTI7IM SYSCFG_C2IMR1_EXTI7IM_Msk

#define	SYSCFG_C2IMR1_EXTI8IM_Pos (24U)

#define	SYSCFG_C2IMR1_EXTI8IM_Msk (0x1UL << SYSCFG_C2IMR1_EXTI8IM_Pos)

#define	SYSCFG_C2IMR1_EXTI8IM SYSCFG_C2IMR1_EXTI8IM_Msk

#define	SYSCFG_C2IMR1_EXTI9IM_Pos (25U)

#define	SYSCFG_C2IMR1_EXTI9IM_Msk (0x1UL << SYSCFG_C2IMR1_EXTI9IM_Pos)

#define	SYSCFG_C2IMR1_EXTI9IM SYSCFG_C2IMR1_EXTI9IM_Msk

#define	SYSCFG_C2IMR1_EXTI10IM_Pos (26U)

#define	SYSCFG_C2IMR1_EXTI10IM_Msk (0x1UL << SYSCFG_C2IMR1_EXTI10IM_Pos)

#define	SYSCFG_C2IMR1_EXTI10IM SYSCFG_C2IMR1_EXTI10IM_Msk

#define	SYSCFG_C2IMR1_EXTI11IM_Pos (27U)

#define	SYSCFG_C2IMR1_EXTI11IM_Msk (0x1UL << SYSCFG_C2IMR1_EXTI11IM_Pos)

#define	SYSCFG_C2IMR1_EXTI11IM SYSCFG_C2IMR1_EXTI11IM_Msk

#define	SYSCFG_C2IMR1_EXTI12IM_Pos (28U)

#define	SYSCFG_C2IMR1_EXTI12IM_Msk (0x1UL << SYSCFG_C2IMR1_EXTI12IM_Pos)

#define	SYSCFG_C2IMR1_EXTI12IM SYSCFG_C2IMR1_EXTI12IM_Msk

#define	SYSCFG_C2IMR1_EXTI13IM_Pos (29U)

#define	SYSCFG_C2IMR1_EXTI13IM_Msk (0x1UL << SYSCFG_C2IMR1_EXTI13IM_Pos)

#define	SYSCFG_C2IMR1_EXTI13IM SYSCFG_C2IMR1_EXTI13IM_Msk

#define	SYSCFG_C2IMR1_EXTI14IM_Pos (30U)

#define	SYSCFG_C2IMR1_EXTI14IM_Msk (0x1UL << SYSCFG_C2IMR1_EXTI14IM_Pos)

#define	SYSCFG_C2IMR1_EXTI14IM SYSCFG_C2IMR1_EXTI14IM_Msk

#define	SYSCFG_C2IMR1_EXTI15IM_Pos (31U)

#define	SYSCFG_C2IMR1_EXTI15IM_Msk (0x1UL << SYSCFG_C2IMR1_EXTI15IM_Pos)

#define	SYSCFG_C2IMR1_EXTI15IM SYSCFG_C2IMR1_EXTI15IM_Msk

#define	SYSCFG_C2IMR2_DMA1CH1IM_Pos (0U)

#define	SYSCFG_C2IMR2_DMA1CH1IM_Msk (0x1UL << SYSCFG_C2IMR2_DMA1CH1IM_Pos)

#define	SYSCFG_C2IMR2_DMA1CH1IM SYSCFG_C2IMR2_DMA1CH1IM_Msk

#define	SYSCFG_C2IMR2_DMA1CH2IM_Pos (1U)

#define	SYSCFG_C2IMR2_DMA1CH2IM_Msk (0x1UL << SYSCFG_C2IMR2_DMA1CH2IM_Pos)

#define	SYSCFG_C2IMR2_DMA1CH2IM SYSCFG_C2IMR2_DMA1CH2IM_Msk

#define	SYSCFG_C2IMR2_DMA1CH3IM_Pos (2U)

#define	SYSCFG_C2IMR2_DMA1CH3IM_Msk (0x1UL << SYSCFG_C2IMR2_DMA1CH3IM_Pos)

#define	SYSCFG_C2IMR2_DMA1CH3IM SYSCFG_C2IMR2_DMA1CH3IM_Msk

#define	SYSCFG_C2IMR2_DMA1CH4IM_Pos (3U)

#define	SYSCFG_C2IMR2_DMA1CH4IM_Msk (0x1UL << SYSCFG_C2IMR2_DMA1CH4IM_Pos)

#define	SYSCFG_C2IMR2_DMA1CH4IM SYSCFG_C2IMR2_DMA1CH4IM_Msk

#define	SYSCFG_C2IMR2_DMA1CH5IM_Pos (4U)

#define	SYSCFG_C2IMR2_DMA1CH5IM_Msk (0x1UL << SYSCFG_C2IMR2_DMA1CH5IM_Pos)

#define	SYSCFG_C2IMR2_DMA1CH5IM SYSCFG_C2IMR2_DMA1CH5IM_Msk

#define	SYSCFG_C2IMR2_DMA1CH6IM_Pos (5U)

#define	SYSCFG_C2IMR2_DMA1CH6IM_Msk (0x1UL << SYSCFG_C2IMR2_DMA1CH6IM_Pos)

#define	SYSCFG_C2IMR2_DMA1CH6IM SYSCFG_C2IMR2_DMA1CH6IM_Msk

#define	SYSCFG_C2IMR2_DMA1CH7IM_Pos (6U)

#define	SYSCFG_C2IMR2_DMA1CH7IM_Msk (0x1UL << SYSCFG_C2IMR2_DMA1CH7IM_Pos)

#define	SYSCFG_C2IMR2_DMA1CH7IM SYSCFG_C2IMR2_DMA1CH7IM_Msk

#define	SYSCFG_C2IMR2_DMA2CH1IM_Pos (8U)

#define	SYSCFG_C2IMR2_DMA2CH1IM_Msk (0x1UL << SYSCFG_C2IMR2_DMA2CH1IM_Pos)

#define	SYSCFG_C2IMR2_DMA2CH1IM SYSCFG_C2IMR2_DMA2CH1IM_Msk

#define	SYSCFG_C2IMR2_DMA2CH2IM_Pos (9U)

#define	SYSCFG_C2IMR2_DMA2CH2IM_Msk (0x1UL << SYSCFG_C2IMR2_DMA2CH2IM_Pos)

#define	SYSCFG_C2IMR2_DMA2CH2IM SYSCFG_C2IMR2_DMA2CH2IM_Msk

#define	SYSCFG_C2IMR2_DMA2CH3IM_Pos (10U)

#define	SYSCFG_C2IMR2_DMA2CH3IM_Msk (0x1UL << SYSCFG_C2IMR2_DMA2CH3IM_Pos)

#define	SYSCFG_C2IMR2_DMA2CH3IM SYSCFG_C2IMR2_DMA2CH3IM_Msk

#define	SYSCFG_C2IMR2_DMA2CH4IM_Pos (11U)

#define	SYSCFG_C2IMR2_DMA2CH4IM_Msk (0x1UL << SYSCFG_C2IMR2_DMA2CH4IM_Pos)

#define	SYSCFG_C2IMR2_DMA2CH4IM SYSCFG_C2IMR2_DMA2CH4IM_Msk

#define	SYSCFG_C2IMR2_DMA2CH5IM_Pos (12U)

#define	SYSCFG_C2IMR2_DMA2CH5IM_Msk (0x1UL << SYSCFG_C2IMR2_DMA2CH5IM_Pos)

#define	SYSCFG_C2IMR2_DMA2CH5IM SYSCFG_C2IMR2_DMA2CH5IM_Msk

#define	SYSCFG_C2IMR2_DMA2CH6IM_Pos (13U)

#define	SYSCFG_C2IMR2_DMA2CH6IM_Msk (0x1UL << SYSCFG_C2IMR2_DMA2CH6IM_Pos)

#define	SYSCFG_C2IMR2_DMA2CH6IM SYSCFG_C2IMR2_DMA2CH6IM_Msk

#define	SYSCFG_C2IMR2_DMA2CH7IM_Pos (14U)

#define	SYSCFG_C2IMR2_DMA2CH7IM_Msk (0x1UL << SYSCFG_C2IMR2_DMA2CH7IM_Pos)

#define	SYSCFG_C2IMR2_DMA2CH7IM SYSCFG_C2IMR2_DMA2CH7IM_Msk

#define	SYSCFG_C2IMR2_DMAMUX1IM_Pos (15U)

#define	SYSCFG_C2IMR2_DMAMUX1IM_Msk (0x1UL << SYSCFG_C2IMR2_DMAMUX1IM_Pos)

#define	SYSCFG_C2IMR2_DMAMUX1IM SYSCFG_C2IMR2_DMAMUX1IM_Msk

#define	SYSCFG_C2IMR2_PVM3IM_Pos (18U)

#define	SYSCFG_C2IMR2_PVM3IM_Msk (0x1UL << SYSCFG_C2IMR2_PVM3IM_Pos)

#define	SYSCFG_C2IMR2_PVM3IM SYSCFG_C2IMR2_PVM3IM_Msk

#define	SYSCFG_C2IMR2_PVDIM_Pos (20U)

#define	SYSCFG_C2IMR2_PVDIM_Msk (0x1UL << SYSCFG_C2IMR2_PVDIM_Pos)

#define	SYSCFG_C2IMR2_PVDIM SYSCFG_C2IMR2_PVDIM_Msk

#define	SYSCFG_RFDCR_RFTBSEL_Pos (0U)

#define	SYSCFG_RFDCR_RFTBSEL_Msk (0x1UL << SYSCFG_RFDCR_RFTBSEL_Pos)

#define	SYSCFG_RFDCR_RFTBSEL SYSCFG_RFDCR_RFTBSEL_Msk

#define	I2C_CR1_PE_Pos (0U)

#define	I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)

#define	I2C_CR1_PE I2C_CR1_PE_Msk

#define	I2C_CR1_TXIE_Pos (1U)

#define	I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos)

#define	I2C_CR1_TXIE I2C_CR1_TXIE_Msk

#define	I2C_CR1_RXIE_Pos (2U)

#define	I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos)

#define	I2C_CR1_RXIE I2C_CR1_RXIE_Msk

#define	I2C_CR1_ADDRIE_Pos (3U)

#define	I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos)

#define	I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk

#define	I2C_CR1_NACKIE_Pos (4U)

#define	I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos)

#define	I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk

#define	I2C_CR1_STOPIE_Pos (5U)

#define	I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos)

#define	I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk

#define	I2C_CR1_TCIE_Pos (6U)

#define	I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos)

#define	I2C_CR1_TCIE I2C_CR1_TCIE_Msk

#define	I2C_CR1_ERRIE_Pos (7U)

#define	I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos)

#define	I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk

#define	I2C_CR1_DNF_Pos (8U)

#define	I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos)

#define	I2C_CR1_DNF I2C_CR1_DNF_Msk

#define	I2C_CR1_ANFOFF_Pos (12U)

#define	I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos)

#define	I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk

#define	I2C_CR1_TXDMAEN_Pos (14U)

#define	I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos)

#define	I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk

#define	I2C_CR1_RXDMAEN_Pos (15U)

#define	I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos)

#define	I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk

#define	I2C_CR1_SBC_Pos (16U)

#define	I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos)

#define	I2C_CR1_SBC I2C_CR1_SBC_Msk

#define	I2C_CR1_NOSTRETCH_Pos (17U)

#define	I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)

#define	I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk

#define	I2C_CR1_WUPEN_Pos (18U)

#define	I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos)

#define	I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk

#define	I2C_CR1_GCEN_Pos (19U)

#define	I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos)

#define	I2C_CR1_GCEN I2C_CR1_GCEN_Msk

#define	I2C_CR1_SMBHEN_Pos (20U)

#define	I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos)

#define	I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk

#define	I2C_CR1_SMBDEN_Pos (21U)

#define	I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos)

#define	I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk

#define	I2C_CR1_ALERTEN_Pos (22U)

#define	I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos)

#define	I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk

#define	I2C_CR1_PECEN_Pos (23U)

#define	I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos)

#define	I2C_CR1_PECEN I2C_CR1_PECEN_Msk

#define	I2C_CR2_SADD_Pos (0U)

#define	I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos)

#define	I2C_CR2_SADD I2C_CR2_SADD_Msk

#define	I2C_CR2_RD_WRN_Pos (10U)

#define	I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos)

#define	I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk

#define	I2C_CR2_ADD10_Pos (11U)

#define	I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos)

#define	I2C_CR2_ADD10 I2C_CR2_ADD10_Msk

#define	I2C_CR2_HEAD10R_Pos (12U)

#define	I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos)

#define	I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk

#define	I2C_CR2_START_Pos (13U)

#define	I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos)

#define	I2C_CR2_START I2C_CR2_START_Msk

#define	I2C_CR2_STOP_Pos (14U)

#define	I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos)

#define	I2C_CR2_STOP I2C_CR2_STOP_Msk

#define	I2C_CR2_NACK_Pos (15U)

#define	I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos)

#define	I2C_CR2_NACK I2C_CR2_NACK_Msk

#define	I2C_CR2_NBYTES_Pos (16U)

#define	I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos)

#define	I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk

#define	I2C_CR2_RELOAD_Pos (24U)

#define	I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos)

#define	I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk

#define	I2C_CR2_AUTOEND_Pos (25U)

#define	I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos)

#define	I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk

#define	I2C_CR2_PECBYTE_Pos (26U)

#define	I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos)

#define	I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk

#define	I2C_OAR1_OA1_Pos (0U)

#define	I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos)

#define	I2C_OAR1_OA1 I2C_OAR1_OA1_Msk

#define	I2C_OAR1_OA1MODE_Pos (10U)

#define	I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos)

#define	I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk

#define	I2C_OAR1_OA1EN_Pos (15U)

#define	I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos)

#define	I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk

#define	I2C_OAR2_OA2_Pos (1U)

#define	I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos)

#define	I2C_OAR2_OA2 I2C_OAR2_OA2_Msk

#define	I2C_OAR2_OA2MSK_Pos (8U)

#define	I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos)

#define	I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk

#define	I2C_OAR2_OA2NOMASK (0x00000000UL)

#define	I2C_OAR2_OA2MASK01_Pos (8U)

#define	I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos)

#define	I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk

#define	I2C_OAR2_OA2MASK02_Pos (9U)

#define	I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos)

#define	I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk

#define	I2C_OAR2_OA2MASK03_Pos (8U)

#define	I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos)

#define	I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk

#define	I2C_OAR2_OA2MASK04_Pos (10U)

#define	I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos)

#define	I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk

#define	I2C_OAR2_OA2MASK05_Pos (8U)

#define	I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos)

#define	I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk

#define	I2C_OAR2_OA2MASK06_Pos (9U)

#define	I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos)

#define	I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk

#define	I2C_OAR2_OA2MASK07_Pos (8U)

#define	I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos)

#define	I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk

#define	I2C_OAR2_OA2EN_Pos (15U)

#define	I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos)

#define	I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk

#define	I2C_TIMINGR_SCLL_Pos (0U)

#define	I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos)

#define	I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk

#define	I2C_TIMINGR_SCLH_Pos (8U)

#define	I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos)

#define	I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk

#define	I2C_TIMINGR_SDADEL_Pos (16U)

#define	I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos)

#define	I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk

#define	I2C_TIMINGR_SCLDEL_Pos (20U)

#define	I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos)

#define	I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk

#define	I2C_TIMINGR_PRESC_Pos (28U)

#define	I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos)

#define	I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk

#define	I2C_TIMEOUTR_TIMEOUTA_Pos (0U)

#define	I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)

#define	I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk

#define	I2C_TIMEOUTR_TIDLE_Pos (12U)

#define	I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)

#define	I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk

#define	I2C_TIMEOUTR_TIMOUTEN_Pos (15U)

#define	I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)

#define	I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk

#define	I2C_TIMEOUTR_TIMEOUTB_Pos (16U)

#define	I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)

#define	I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk

#define	I2C_TIMEOUTR_TEXTEN_Pos (31U)

#define	I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)

#define	I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk

#define	I2C_ISR_TXE_Pos (0U)

#define	I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos)

#define	I2C_ISR_TXE I2C_ISR_TXE_Msk

#define	I2C_ISR_TXIS_Pos (1U)

#define	I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos)

#define	I2C_ISR_TXIS I2C_ISR_TXIS_Msk

#define	I2C_ISR_RXNE_Pos (2U)

#define	I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos)

#define	I2C_ISR_RXNE I2C_ISR_RXNE_Msk

#define	I2C_ISR_ADDR_Pos (3U)

#define	I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos)

#define	I2C_ISR_ADDR I2C_ISR_ADDR_Msk

#define	I2C_ISR_NACKF_Pos (4U)

#define	I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos)

#define	I2C_ISR_NACKF I2C_ISR_NACKF_Msk

#define	I2C_ISR_STOPF_Pos (5U)

#define	I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos)

#define	I2C_ISR_STOPF I2C_ISR_STOPF_Msk

#define	I2C_ISR_TC_Pos (6U)

#define	I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos)

#define	I2C_ISR_TC I2C_ISR_TC_Msk

#define	I2C_ISR_TCR_Pos (7U)

#define	I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos)

#define	I2C_ISR_TCR I2C_ISR_TCR_Msk

#define	I2C_ISR_BERR_Pos (8U)

#define	I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos)

#define	I2C_ISR_BERR I2C_ISR_BERR_Msk

#define	I2C_ISR_ARLO_Pos (9U)

#define	I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos)

#define	I2C_ISR_ARLO I2C_ISR_ARLO_Msk

#define	I2C_ISR_OVR_Pos (10U)

#define	I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos)

#define	I2C_ISR_OVR I2C_ISR_OVR_Msk

#define	I2C_ISR_PECERR_Pos (11U)

#define	I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos)

#define	I2C_ISR_PECERR I2C_ISR_PECERR_Msk

#define	I2C_ISR_TIMEOUT_Pos (12U)

#define	I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos)

#define	I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk

#define	I2C_ISR_ALERT_Pos (13U)

#define	I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos)

#define	I2C_ISR_ALERT I2C_ISR_ALERT_Msk

#define	I2C_ISR_BUSY_Pos (15U)

#define	I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos)

#define	I2C_ISR_BUSY I2C_ISR_BUSY_Msk

#define	I2C_ISR_DIR_Pos (16U)

#define	I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos)

#define	I2C_ISR_DIR I2C_ISR_DIR_Msk

#define	I2C_ISR_ADDCODE_Pos (17U)

#define	I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos)

#define	I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk

#define	I2C_ICR_ADDRCF_Pos (3U)

#define	I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos)

#define	I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk

#define	I2C_ICR_NACKCF_Pos (4U)

#define	I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos)

#define	I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk

#define	I2C_ICR_STOPCF_Pos (5U)

#define	I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos)

#define	I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk

#define	I2C_ICR_BERRCF_Pos (8U)

#define	I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos)

#define	I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk

#define	I2C_ICR_ARLOCF_Pos (9U)

#define	I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos)

#define	I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk

#define	I2C_ICR_OVRCF_Pos (10U)

#define	I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos)

#define	I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk

#define	I2C_ICR_PECCF_Pos (11U)

#define	I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos)

#define	I2C_ICR_PECCF I2C_ICR_PECCF_Msk

#define	I2C_ICR_TIMOUTCF_Pos (12U)

#define	I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos)

#define	I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk

#define	I2C_ICR_ALERTCF_Pos (13U)

#define	I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos)

#define	I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk

#define	I2C_PECR_PEC_Pos (0U)

#define	I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos)

#define	I2C_PECR_PEC I2C_PECR_PEC_Msk

#define	I2C_RXDR_RXDATA_Pos (0U)

#define	I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos)

#define	I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk

#define	I2C_TXDR_TXDATA_Pos (0U)

#define	I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos)

#define	I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk

#define	IPCC_C1CR_RXOIE_Pos (0U)

#define	IPCC_C1CR_RXOIE_Msk (0x1UL << IPCC_C1CR_RXOIE_Pos)

#define	IPCC_C1CR_RXOIE IPCC_C1CR_RXOIE_Msk

#define	IPCC_C1CR_TXFIE_Pos (16U)

#define	IPCC_C1CR_TXFIE_Msk (0x1UL << IPCC_C1CR_TXFIE_Pos)

#define	IPCC_C1CR_TXFIE IPCC_C1CR_TXFIE_Msk

#define	IPCC_C1MR_CH1OM_Pos (0U)

#define	IPCC_C1MR_CH1OM_Msk (0x1UL << IPCC_C1MR_CH1OM_Pos)

#define	IPCC_C1MR_CH1OM IPCC_C1MR_CH1OM_Msk

#define	IPCC_C1MR_CH2OM_Pos (1U)

#define	IPCC_C1MR_CH2OM_Msk (0x1UL << IPCC_C1MR_CH2OM_Pos)

#define	IPCC_C1MR_CH2OM IPCC_C1MR_CH2OM_Msk

#define	IPCC_C1MR_CH3OM_Pos (2U)

#define	IPCC_C1MR_CH3OM_Msk (0x1UL << IPCC_C1MR_CH3OM_Pos)

#define	IPCC_C1MR_CH3OM IPCC_C1MR_CH3OM_Msk

#define	IPCC_C1MR_CH4OM_Pos (3U)

#define	IPCC_C1MR_CH4OM_Msk (0x1UL << IPCC_C1MR_CH4OM_Pos)

#define	IPCC_C1MR_CH4OM IPCC_C1MR_CH4OM_Msk

#define	IPCC_C1MR_CH5OM_Pos (4U)

#define	IPCC_C1MR_CH5OM_Msk (0x1UL << IPCC_C1MR_CH5OM_Pos)

#define	IPCC_C1MR_CH5OM IPCC_C1MR_CH5OM_Msk

#define	IPCC_C1MR_CH6OM_Pos (5U)

#define	IPCC_C1MR_CH6OM_Msk (0x1UL << IPCC_C1MR_CH6OM_Pos)

#define	IPCC_C1MR_CH6OM IPCC_C1MR_CH6OM_Msk

#define	IPCC_C1MR_CH1FM_Pos (16U)

#define	IPCC_C1MR_CH1FM_Msk (0x1UL << IPCC_C1MR_CH1FM_Pos)

#define	IPCC_C1MR_CH1FM IPCC_C1MR_CH1FM_Msk

#define	IPCC_C1MR_CH2FM_Pos (17U)

#define	IPCC_C1MR_CH2FM_Msk (0x1UL << IPCC_C1MR_CH2FM_Pos)

#define	IPCC_C1MR_CH2FM IPCC_C1MR_CH2FM_Msk

#define	IPCC_C1MR_CH3FM_Pos (18U)

#define	IPCC_C1MR_CH3FM_Msk (0x1UL << IPCC_C1MR_CH3FM_Pos)

#define	IPCC_C1MR_CH3FM IPCC_C1MR_CH3FM_Msk

#define	IPCC_C1MR_CH4FM_Pos (19U)

#define	IPCC_C1MR_CH4FM_Msk (0x1UL << IPCC_C1MR_CH4FM_Pos)

#define	IPCC_C1MR_CH4FM IPCC_C1MR_CH4FM_Msk

#define	IPCC_C1MR_CH5FM_Pos (20U)

#define	IPCC_C1MR_CH5FM_Msk (0x1UL << IPCC_C1MR_CH5FM_Pos)

#define	IPCC_C1MR_CH5FM IPCC_C1MR_CH5FM_Msk

#define	IPCC_C1MR_CH6FM_Pos (21U)

#define	IPCC_C1MR_CH6FM_Msk (0x1UL << IPCC_C1MR_CH6FM_Pos)

#define	IPCC_C1MR_CH6FM IPCC_C1MR_CH6FM_Msk

#define	IPCC_C1SCR_CH1C_Pos (0U)

#define	IPCC_C1SCR_CH1C_Msk (0x1UL << IPCC_C1SCR_CH1C_Pos)

#define	IPCC_C1SCR_CH1C IPCC_C1SCR_CH1C_Msk

#define	IPCC_C1SCR_CH2C_Pos (1U)

#define	IPCC_C1SCR_CH2C_Msk (0x1UL << IPCC_C1SCR_CH2C_Pos)

#define	IPCC_C1SCR_CH2C IPCC_C1SCR_CH2C_Msk

#define	IPCC_C1SCR_CH3C_Pos (2U)

#define	IPCC_C1SCR_CH3C_Msk (0x1UL << IPCC_C1SCR_CH3C_Pos)

#define	IPCC_C1SCR_CH3C IPCC_C1SCR_CH3C_Msk

#define	IPCC_C1SCR_CH4C_Pos (3U)

#define	IPCC_C1SCR_CH4C_Msk (0x1UL << IPCC_C1SCR_CH4C_Pos)

#define	IPCC_C1SCR_CH4C IPCC_C1SCR_CH4C_Msk

#define	IPCC_C1SCR_CH5C_Pos (4U)

#define	IPCC_C1SCR_CH5C_Msk (0x1UL << IPCC_C1SCR_CH5C_Pos)

#define	IPCC_C1SCR_CH5C IPCC_C1SCR_CH5C_Msk

#define	IPCC_C1SCR_CH6C_Pos (5U)

#define	IPCC_C1SCR_CH6C_Msk (0x1UL << IPCC_C1SCR_CH6C_Pos)

#define	IPCC_C1SCR_CH6C IPCC_C1SCR_CH6C_Msk

#define	IPCC_C1SCR_CH1S_Pos (16U)

#define	IPCC_C1SCR_CH1S_Msk (0x1UL << IPCC_C1SCR_CH1S_Pos)

#define	IPCC_C1SCR_CH1S IPCC_C1SCR_CH1S_Msk

#define	IPCC_C1SCR_CH2S_Pos (17U)

#define	IPCC_C1SCR_CH2S_Msk (0x1UL << IPCC_C1SCR_CH2S_Pos)

#define	IPCC_C1SCR_CH2S IPCC_C1SCR_CH2S_Msk

#define	IPCC_C1SCR_CH3S_Pos (18U)

#define	IPCC_C1SCR_CH3S_Msk (0x1UL << IPCC_C1SCR_CH3S_Pos)

#define	IPCC_C1SCR_CH3S IPCC_C1SCR_CH3S_Msk

#define	IPCC_C1SCR_CH4S_Pos (19U)

#define	IPCC_C1SCR_CH4S_Msk (0x1UL << IPCC_C1SCR_CH4S_Pos)

#define	IPCC_C1SCR_CH4S IPCC_C1SCR_CH4S_Msk

#define	IPCC_C1SCR_CH5S_Pos (20U)

#define	IPCC_C1SCR_CH5S_Msk (0x1UL << IPCC_C1SCR_CH5S_Pos)

#define	IPCC_C1SCR_CH5S IPCC_C1SCR_CH5S_Msk

#define	IPCC_C1SCR_CH6S_Pos (21U)

#define	IPCC_C1SCR_CH6S_Msk (0x1UL << IPCC_C1SCR_CH6S_Pos)

#define	IPCC_C1SCR_CH6S IPCC_C1SCR_CH6S_Msk

#define	IPCC_C1TOC2SR_CH1F_Pos (0U)

#define	IPCC_C1TOC2SR_CH1F_Msk (0x1UL << IPCC_C1TOC2SR_CH1F_Pos)

#define	IPCC_C1TOC2SR_CH1F IPCC_C1TOC2SR_CH1F_Msk

#define	IPCC_C1TOC2SR_CH2F_Pos (1U)

#define	IPCC_C1TOC2SR_CH2F_Msk (0x1UL << IPCC_C1TOC2SR_CH2F_Pos)

#define	IPCC_C1TOC2SR_CH2F IPCC_C1TOC2SR_CH2F_Msk

#define	IPCC_C1TOC2SR_CH3F_Pos (2U)

#define	IPCC_C1TOC2SR_CH3F_Msk (0x1UL << IPCC_C1TOC2SR_CH3F_Pos)

#define	IPCC_C1TOC2SR_CH3F IPCC_C1TOC2SR_CH3F_Msk

#define	IPCC_C1TOC2SR_CH4F_Pos (3U)

#define	IPCC_C1TOC2SR_CH4F_Msk (0x1UL << IPCC_C1TOC2SR_CH4F_Pos)

#define	IPCC_C1TOC2SR_CH4F IPCC_C1TOC2SR_CH4F_Msk

#define	IPCC_C1TOC2SR_CH5F_Pos (4U)

#define	IPCC_C1TOC2SR_CH5F_Msk (0x1UL << IPCC_C1TOC2SR_CH5F_Pos)

#define	IPCC_C1TOC2SR_CH5F IPCC_C1TOC2SR_CH5F_Msk

#define	IPCC_C1TOC2SR_CH6F_Pos (5U)

#define	IPCC_C1TOC2SR_CH6F_Msk (0x1UL << IPCC_C1TOC2SR_CH6F_Pos)

#define	IPCC_C1TOC2SR_CH6F IPCC_C1TOC2SR_CH6F_Msk

#define	IPCC_C2CR_RXOIE_Pos (0U)

#define	IPCC_C2CR_RXOIE_Msk (0x1UL << IPCC_C2CR_RXOIE_Pos)

#define	IPCC_C2CR_RXOIE IPCC_C2CR_RXOIE_Msk

#define	IPCC_C2CR_TXFIE_Pos (16U)

#define	IPCC_C2CR_TXFIE_Msk (0x1UL << IPCC_C2CR_TXFIE_Pos)

#define	IPCC_C2CR_TXFIE IPCC_C2CR_TXFIE_Msk

#define	IPCC_C2MR_CH1OM_Pos (0U)

#define	IPCC_C2MR_CH1OM_Msk (0x1UL << IPCC_C2MR_CH1OM_Pos)

#define	IPCC_C2MR_CH1OM IPCC_C2MR_CH1OM_Msk

#define	IPCC_C2MR_CH2OM_Pos (1U)

#define	IPCC_C2MR_CH2OM_Msk (0x1UL << IPCC_C2MR_CH2OM_Pos)

#define	IPCC_C2MR_CH2OM IPCC_C2MR_CH2OM_Msk

#define	IPCC_C2MR_CH3OM_Pos (2U)

#define	IPCC_C2MR_CH3OM_Msk (0x1UL << IPCC_C2MR_CH3OM_Pos)

#define	IPCC_C2MR_CH3OM IPCC_C2MR_CH3OM_Msk

#define	IPCC_C2MR_CH4OM_Pos (3U)

#define	IPCC_C2MR_CH4OM_Msk (0x1UL << IPCC_C2MR_CH4OM_Pos)

#define	IPCC_C2MR_CH4OM IPCC_C2MR_CH4OM_Msk

#define	IPCC_C2MR_CH5OM_Pos (4U)

#define	IPCC_C2MR_CH5OM_Msk (0x1UL << IPCC_C2MR_CH5OM_Pos)

#define	IPCC_C2MR_CH5OM IPCC_C2MR_CH5OM_Msk

#define	IPCC_C2MR_CH6OM_Pos (5U)

#define	IPCC_C2MR_CH6OM_Msk (0x1UL << IPCC_C2MR_CH6OM_Pos)

#define	IPCC_C2MR_CH6OM IPCC_C2MR_CH6OM_Msk

#define	IPCC_C2MR_CH1FM_Pos (16U)

#define	IPCC_C2MR_CH1FM_Msk (0x1UL << IPCC_C2MR_CH1FM_Pos)

#define	IPCC_C2MR_CH1FM IPCC_C2MR_CH1FM_Msk

#define	IPCC_C2MR_CH2FM_Pos (17U)

#define	IPCC_C2MR_CH2FM_Msk (0x1UL << IPCC_C2MR_CH2FM_Pos)

#define	IPCC_C2MR_CH2FM IPCC_C2MR_CH2FM_Msk

#define	IPCC_C2MR_CH3FM_Pos (18U)

#define	IPCC_C2MR_CH3FM_Msk (0x1UL << IPCC_C2MR_CH3FM_Pos)

#define	IPCC_C2MR_CH3FM IPCC_C2MR_CH3FM_Msk

#define	IPCC_C2MR_CH4FM_Pos (19U)

#define	IPCC_C2MR_CH4FM_Msk (0x1UL << IPCC_C2MR_CH4FM_Pos)

#define	IPCC_C2MR_CH4FM IPCC_C2MR_CH4FM_Msk

#define	IPCC_C2MR_CH5FM_Pos (20U)

#define	IPCC_C2MR_CH5FM_Msk (0x1UL << IPCC_C2MR_CH5FM_Pos)

#define	IPCC_C2MR_CH5FM IPCC_C2MR_CH5FM_Msk

#define	IPCC_C2MR_CH6FM_Pos (21U)

#define	IPCC_C2MR_CH6FM_Msk (0x1UL << IPCC_C2MR_CH6FM_Pos)

#define	IPCC_C2MR_CH6FM IPCC_C2MR_CH6FM_Msk

#define	IPCC_C2SCR_CH1C_Pos (0U)

#define	IPCC_C2SCR_CH1C_Msk (0x1UL << IPCC_C2SCR_CH1C_Pos)

#define	IPCC_C2SCR_CH1C IPCC_C2SCR_CH1C_Msk

#define	IPCC_C2SCR_CH2C_Pos (1U)

#define	IPCC_C2SCR_CH2C_Msk (0x1UL << IPCC_C2SCR_CH2C_Pos)

#define	IPCC_C2SCR_CH2C IPCC_C2SCR_CH2C_Msk

#define	IPCC_C2SCR_CH3C_Pos (2U)

#define	IPCC_C2SCR_CH3C_Msk (0x1UL << IPCC_C2SCR_CH3C_Pos)

#define	IPCC_C2SCR_CH3C IPCC_C2SCR_CH3C_Msk

#define	IPCC_C2SCR_CH4C_Pos (3U)

#define	IPCC_C2SCR_CH4C_Msk (0x1UL << IPCC_C2SCR_CH4C_Pos)

#define	IPCC_C2SCR_CH4C IPCC_C2SCR_CH4C_Msk

#define	IPCC_C2SCR_CH5C_Pos (4U)

#define	IPCC_C2SCR_CH5C_Msk (0x1UL << IPCC_C2SCR_CH5C_Pos)

#define	IPCC_C2SCR_CH5C IPCC_C2SCR_CH5C_Msk

#define	IPCC_C2SCR_CH6C_Pos (5U)

#define	IPCC_C2SCR_CH6C_Msk (0x1UL << IPCC_C2SCR_CH6C_Pos)

#define	IPCC_C2SCR_CH6C IPCC_C2SCR_CH6C_Msk

#define	IPCC_C2SCR_CH1S_Pos (16U)

#define	IPCC_C2SCR_CH1S_Msk (0x1UL << IPCC_C2SCR_CH1S_Pos)

#define	IPCC_C2SCR_CH1S IPCC_C2SCR_CH1S_Msk

#define	IPCC_C2SCR_CH2S_Pos (17U)

#define	IPCC_C2SCR_CH2S_Msk (0x1UL << IPCC_C2SCR_CH2S_Pos)

#define	IPCC_C2SCR_CH2S IPCC_C2SCR_CH2S_Msk

#define	IPCC_C2SCR_CH3S_Pos (18U)

#define	IPCC_C2SCR_CH3S_Msk (0x1UL << IPCC_C2SCR_CH3S_Pos)

#define	IPCC_C2SCR_CH3S IPCC_C2SCR_CH3S_Msk

#define	IPCC_C2SCR_CH4S_Pos (19U)

#define	IPCC_C2SCR_CH4S_Msk (0x1UL << IPCC_C2SCR_CH4S_Pos)

#define	IPCC_C2SCR_CH4S IPCC_C2SCR_CH4S_Msk

#define	IPCC_C2SCR_CH5S_Pos (20U)

#define	IPCC_C2SCR_CH5S_Msk (0x1UL << IPCC_C2SCR_CH5S_Pos)

#define	IPCC_C2SCR_CH5S IPCC_C2SCR_CH5S_Msk

#define	IPCC_C2SCR_CH6S_Pos (21U)

#define	IPCC_C2SCR_CH6S_Msk (0x1UL << IPCC_C2SCR_CH6S_Pos)

#define	IPCC_C2SCR_CH6S IPCC_C2SCR_CH6S_Msk

#define	IPCC_C2TOC1SR_CH1F_Pos (0U)

#define	IPCC_C2TOC1SR_CH1F_Msk (0x1UL << IPCC_C2TOC1SR_CH1F_Pos)

#define	IPCC_C2TOC1SR_CH1F IPCC_C2TOC1SR_CH1F_Msk

#define	IPCC_C2TOC1SR_CH2F_Pos (1U)

#define	IPCC_C2TOC1SR_CH2F_Msk (0x1UL << IPCC_C2TOC1SR_CH2F_Pos)

#define	IPCC_C2TOC1SR_CH2F IPCC_C2TOC1SR_CH2F_Msk

#define	IPCC_C2TOC1SR_CH3F_Pos (2U)

#define	IPCC_C2TOC1SR_CH3F_Msk (0x1UL << IPCC_C2TOC1SR_CH3F_Pos)

#define	IPCC_C2TOC1SR_CH3F IPCC_C2TOC1SR_CH3F_Msk

#define	IPCC_C2TOC1SR_CH4F_Pos (3U)

#define	IPCC_C2TOC1SR_CH4F_Msk (0x1UL << IPCC_C2TOC1SR_CH4F_Pos)

#define	IPCC_C2TOC1SR_CH4F IPCC_C2TOC1SR_CH4F_Msk

#define	IPCC_C2TOC1SR_CH5F_Pos (4U)

#define	IPCC_C2TOC1SR_CH5F_Msk (0x1UL << IPCC_C2TOC1SR_CH5F_Pos)

#define	IPCC_C2TOC1SR_CH5F IPCC_C2TOC1SR_CH5F_Msk

#define	IPCC_C2TOC1SR_CH6F_Pos (5U)

#define	IPCC_C2TOC1SR_CH6F_Msk (0x1UL << IPCC_C2TOC1SR_CH6F_Pos)

#define	IPCC_C2TOC1SR_CH6F IPCC_C2TOC1SR_CH6F_Msk

#define	IPCC_CR_RXOIE_Pos IPCC_C1CR_RXOIE_Pos

#define	IPCC_CR_RXOIE_Msk IPCC_C1CR_RXOIE_Msk

#define	IPCC_CR_RXOIE IPCC_C1CR_RXOIE

#define	IPCC_CR_TXFIE_Pos IPCC_C1CR_TXFIE_Pos

#define	IPCC_CR_TXFIE_Msk IPCC_C1CR_TXFIE_Msk

#define	IPCC_CR_TXFIE IPCC_C1CR_TXFIE

#define	IPCC_MR_CH1OM_Pos IPCC_C1MR_CH1OM_Pos

#define	IPCC_MR_CH1OM_Msk IPCC_C1MR_CH1OM_Msk

#define	IPCC_MR_CH1OM IPCC_C1MR_CH1OM

#define	IPCC_MR_CH2OM_Pos IPCC_C1MR_CH2OM_Pos

#define	IPCC_MR_CH2OM_Msk IPCC_C1MR_CH2OM_Msk

#define	IPCC_MR_CH2OM IPCC_C1MR_CH2OM

#define	IPCC_MR_CH3OM_Pos IPCC_C1MR_CH3OM_Pos

#define	IPCC_MR_CH3OM_Msk IPCC_C1MR_CH3OM_Msk

#define	IPCC_MR_CH3OM IPCC_C1MR_CH3OM

#define	IPCC_MR_CH4OM_Pos IPCC_C1MR_CH4OM_Pos

#define	IPCC_MR_CH4OM_Msk IPCC_C1MR_CH4OM_Msk

#define	IPCC_MR_CH4OM IPCC_C1MR_CH4OM

#define	IPCC_MR_CH5OM_Pos IPCC_C1MR_CH5OM_Pos

#define	IPCC_MR_CH5OM_Msk IPCC_C1MR_CH5OM_Msk

#define	IPCC_MR_CH5OM IPCC_C1MR_CH5OM

#define	IPCC_MR_CH6OM_Pos IPCC_C1MR_CH6OM_Pos

#define	IPCC_MR_CH6OM_Msk IPCC_C1MR_CH6OM_Msk

#define	IPCC_MR_CH6OM IPCC_C1MR_CH6OM

#define	IPCC_MR_CH1FM_Pos IPCC_C1MR_CH1FM_Pos

#define	IPCC_MR_CH1FM_Msk IPCC_C1MR_CH1FM_Msk

#define	IPCC_MR_CH1FM IPCC_C1MR_CH1FM

#define	IPCC_MR_CH2FM_Pos IPCC_C1MR_CH2FM_Pos

#define	IPCC_MR_CH2FM_Msk IPCC_C1MR_CH2FM_Msk

#define	IPCC_MR_CH2FM IPCC_C1MR_CH2FM

#define	IPCC_MR_CH3FM_Pos IPCC_C1MR_CH3FM_Pos

#define	IPCC_MR_CH3FM_Msk IPCC_C1MR_CH3FM_Msk

#define	IPCC_MR_CH3FM IPCC_C1MR_CH3FM

#define	IPCC_MR_CH4FM_Pos IPCC_C1MR_CH4FM_Pos

#define	IPCC_MR_CH4FM_Msk IPCC_C1MR_CH4FM_Msk

#define	IPCC_MR_CH4FM IPCC_C1MR_CH4FM

#define	IPCC_MR_CH5FM_Pos IPCC_C1MR_CH5FM_Pos

#define	IPCC_MR_CH5FM_Msk IPCC_C1MR_CH5FM_Msk

#define	IPCC_MR_CH5FM IPCC_C1MR_CH5FM

#define	IPCC_MR_CH6FM_Pos IPCC_C1MR_CH6FM_Pos

#define	IPCC_MR_CH6FM_Msk IPCC_C1MR_CH6FM_Msk

#define	IPCC_MR_CH6FM IPCC_C1MR_CH6FM

#define	IPCC_SCR_CH1C_Pos IPCC_C1SCR_CH1C_Pos

#define	IPCC_SCR_CH1C_Msk IPCC_C1SCR_CH1C_Msk

#define	IPCC_SCR_CH1C IPCC_C1SCR_CH1C

#define	IPCC_SCR_CH2C_Pos IPCC_C1SCR_CH2C_Pos

#define	IPCC_SCR_CH2C_Msk IPCC_C1SCR_CH2C_Msk

#define	IPCC_SCR_CH2C IPCC_C1SCR_CH2C

#define	IPCC_SCR_CH3C_Pos IPCC_C1SCR_CH3C_Pos

#define	IPCC_SCR_CH3C_Msk IPCC_C1SCR_CH3C_Msk

#define	IPCC_SCR_CH3C IPCC_C1SCR_CH3C

#define	IPCC_SCR_CH4C_Pos IPCC_C1SCR_CH4C_Pos

#define	IPCC_SCR_CH4C_Msk IPCC_C1SCR_CH4C_Msk

#define	IPCC_SCR_CH4C IPCC_C1SCR_CH4C

#define	IPCC_SCR_CH5C_Pos IPCC_C1SCR_CH5C_Pos

#define	IPCC_SCR_CH5C_Msk IPCC_C1SCR_CH5C_Msk

#define	IPCC_SCR_CH5C IPCC_C1SCR_CH5C

#define	IPCC_SCR_CH6C_Pos IPCC_C1SCR_CH6C_Pos

#define	IPCC_SCR_CH6C_Msk IPCC_C1SCR_CH6C_Msk

#define	IPCC_SCR_CH6C IPCC_C1SCR_CH6C

#define	IPCC_SCR_CH1S_Pos IPCC_C1SCR_CH1S_Pos

#define	IPCC_SCR_CH1S_Msk IPCC_C1SCR_CH1S_Msk

#define	IPCC_SCR_CH1S IPCC_C1SCR_CH1S

#define	IPCC_SCR_CH2S_Pos IPCC_C1SCR_CH2S_Pos

#define	IPCC_SCR_CH2S_Msk IPCC_C1SCR_CH2S_Msk

#define	IPCC_SCR_CH2S IPCC_C1SCR_CH2S

#define	IPCC_SCR_CH3S_Pos IPCC_C1SCR_CH3S_Pos

#define	IPCC_SCR_CH3S_Msk IPCC_C1SCR_CH3S_Msk

#define	IPCC_SCR_CH3S IPCC_C1SCR_CH3S

#define	IPCC_SCR_CH4S_Pos IPCC_C1SCR_CH4S_Pos

#define	IPCC_SCR_CH4S_Msk IPCC_C1SCR_CH4S_Msk

#define	IPCC_SCR_CH4S IPCC_C1SCR_CH4S

#define	IPCC_SCR_CH5S_Pos IPCC_C1SCR_CH5S_Pos

#define	IPCC_SCR_CH5S_Msk IPCC_C1SCR_CH5S_Msk

#define	IPCC_SCR_CH5S IPCC_C1SCR_CH5S

#define	IPCC_SCR_CH6S_Pos IPCC_C1SCR_CH6S_Pos

#define	IPCC_SCR_CH6S_Msk IPCC_C1SCR_CH6S_Msk

#define	IPCC_SCR_CH6S IPCC_C1SCR_CH6S

#define	IPCC_SR_CH1F_Pos IPCC_C1TOC2SR_CH1F_Pos

#define	IPCC_SR_CH1F_Msk IPCC_C1TOC2SR_CH1F_Msk

#define	IPCC_SR_CH1F IPCC_C1TOC2SR_CH1F

#define	IPCC_SR_CH2F_Pos IPCC_C1TOC2SR_CH2F_Pos

#define	IPCC_SR_CH2F_Msk IPCC_C1TOC2SR_CH2F_Msk

#define	IPCC_SR_CH2F IPCC_C1TOC2SR_CH2F

#define	IPCC_SR_CH3F_Pos IPCC_C1TOC2SR_CH3F_Pos

#define	IPCC_SR_CH3F_Msk IPCC_C1TOC2SR_CH3F_Msk

#define	IPCC_SR_CH3F IPCC_C1TOC2SR_CH3F

#define	IPCC_SR_CH4F_Pos IPCC_C1TOC2SR_CH4F_Pos

#define	IPCC_SR_CH4F_Msk IPCC_C1TOC2SR_CH4F_Msk

#define	IPCC_SR_CH4F IPCC_C1TOC2SR_CH4F

#define	IPCC_SR_CH5F_Pos IPCC_C1TOC2SR_CH5F_Pos

#define	IPCC_SR_CH5F_Msk IPCC_C1TOC2SR_CH5F_Msk

#define	IPCC_SR_CH5F IPCC_C1TOC2SR_CH5F

#define	IPCC_SR_CH6F_Pos IPCC_C1TOC2SR_CH6F_Pos

#define	IPCC_SR_CH6F_Msk IPCC_C1TOC2SR_CH6F_Msk

#define	IPCC_SR_CH6F IPCC_C1TOC2SR_CH6F

#define	IPCC_CHANNEL_NUMBER 6U

#define	IWDG_KR_KEY_Pos (0U)

#define	IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)

#define	IWDG_KR_KEY IWDG_KR_KEY_Msk

#define	IWDG_PR_PR_Pos (0U)

#define	IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)

#define	IWDG_PR_PR IWDG_PR_PR_Msk

#define	IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)

#define	IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)

#define	IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)

#define	IWDG_RLR_RL_Pos (0U)

#define	IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)

#define	IWDG_RLR_RL IWDG_RLR_RL_Msk

#define	IWDG_SR_PVU_Pos (0U)

#define	IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)

#define	IWDG_SR_PVU IWDG_SR_PVU_Msk

#define	IWDG_SR_RVU_Pos (1U)

#define	IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)

#define	IWDG_SR_RVU IWDG_SR_RVU_Msk

#define	IWDG_SR_WVU_Pos (2U)

#define	IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos)

#define	IWDG_SR_WVU IWDG_SR_WVU_Msk

#define	IWDG_WINR_WIN_Pos (0U)

#define	IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos)

#define	IWDG_WINR_WIN IWDG_WINR_WIN_Msk

#define	VREFBUF_CSR_ENVR_Pos (0U)

#define	VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos)

#define	VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk

#define	VREFBUF_CSR_HIZ_Pos (1U)

#define	VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos)

#define	VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk

#define	VREFBUF_CSR_VRS_Pos (2U)

#define	VREFBUF_CSR_VRS_Msk (0x1UL << VREFBUF_CSR_VRS_Pos)

#define	VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk

#define	VREFBUF_CSR_VRR_Pos (3U)

#define	VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos)

#define	VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk

#define	VREFBUF_CCR_TRIM_Pos (0U)

#define	VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos)

#define	VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk

#define	WWDG_CR_T_Pos (0U)

#define	WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)

#define	WWDG_CR_T WWDG_CR_T_Msk

#define	WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)

#define	WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)

#define	WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)

#define	WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)

#define	WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)

#define	WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)

#define	WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)

#define	WWDG_CR_WDGA_Pos (7U)

#define	WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)

#define	WWDG_CR_WDGA WWDG_CR_WDGA_Msk

#define	WWDG_CFR_W_Pos (0U)

#define	WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W WWDG_CFR_W_Msk

#define	WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_EWI_Pos (9U)

#define	WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)

#define	WWDG_CFR_EWI WWDG_CFR_EWI_Msk

#define	WWDG_CFR_WDGTB_Pos (11U)

#define	WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos)

#define	WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk

#define	WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)

#define	WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)

#define	WWDG_CFR_WDGTB_2 (0x4UL << WWDG_CFR_WDGTB_Pos)

#define	WWDG_SR_EWIF_Pos (0U)

#define	WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)

#define	WWDG_SR_EWIF WWDG_SR_EWIF_Msk

#define	DBGMCU_IDCODE_DEV_ID_Pos (0U)

#define	DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)

#define	DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk

#define	DBGMCU_IDCODE_REV_ID_Pos (16U)

#define	DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos

#define	DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk

#define	DBGMCU_CR_DBG_SLEEP_Pos (0U)

#define	DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)

#define	DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk

#define	DBGMCU_CR_DBG_STOP_Pos (1U)

#define	DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)

#define	DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk

#define	DBGMCU_CR_DBG_STANDBY_Pos (2U)

#define	DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos

#define	DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk

#define	DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U)

#define	DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)

#define	DBGMCU_APB1FZR1_DBG_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk

#define	DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos (10U)

#define	DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos)

#define	DBGMCU_APB1FZR1_DBG_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk

#define	DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos (11U)

#define	DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos)

#define	DBGMCU_APB1FZR1_DBG_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk

#define	DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos (12U)

#define	DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos)

#define	DBGMCU_APB1FZR1_DBG_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk

#define	DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos (21U)

#define	DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos)

#define	DBGMCU_APB1FZR1_DBG_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk

#define	DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos (22U)

#define	DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos)

#define	DBGMCU_APB1FZR1_DBG_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk

#define	DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos (23U)

#define	DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos)

#define	DBGMCU_APB1FZR1_DBG_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk

#define	DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos (31U)

#define	DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos

#define	DBGMCU_APB1FZR1_DBG_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk

#define	DBGMCU_C2APB1FZR1_DBG_TIM2_STOP_Pos (0U)

#define	DBGMCU_C2APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_C2APB1FZR1_DBG_TIM2_STOP_Pos)

#define	DBGMCU_C2APB1FZR1_DBG_TIM2_STOP DBGMCU_C2APB1FZR1_DBG_TIM2_STOP_Msk

#define	DBGMCU_C2APB1FZR1_DBG_RTC_STOP_Pos (10U)

#define	DBGMCU_C2APB1FZR1_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_C2APB1FZR1_DBG_RTC_STOP_Pos)

#define	DBGMCU_C2APB1FZR1_DBG_RTC_STOP DBGMCU_C2APB1FZR1_DBG_RTC_STOP_Msk

#define	DBGMCU_C2APB1FZR1_DBG_IWDG_STOP_Pos (12U)

#define	DBGMCU_C2APB1FZR1_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_C2APB1FZR1_DBG_IWDG_STOP_Pos)

#define	DBGMCU_C2APB1FZR1_DBG_IWDG_STOP DBGMCU_C2APB1FZR1_DBG_IWDG_STOP_Msk

#define	DBGMCU_C2APB1FZR1_DBG_I2C1_STOP_Pos (21U)

#define	DBGMCU_C2APB1FZR1_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_C2APB1FZR1_DBG_I2C1_STOP_Pos)

#define	DBGMCU_C2APB1FZR1_DBG_I2C1_STOP DBGMCU_C2APB1FZR1_DBG_I2C1_STOP_Msk

#define	DBGMCU_C2APB1FZR1_DBG_I2C2_STOP_Pos (22U)

#define	DBGMCU_C2APB1FZR1_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_C2APB1FZR1_DBG_I2C2_STOP_Pos)

#define	DBGMCU_C2APB1FZR1_DBG_I2C2_STOP DBGMCU_C2APB1FZR1_DBG_I2C2_STOP_Msk

#define	DBGMCU_C2APB1FZR1_DBG_I2C3_STOP_Pos (23U)

#define	DBGMCU_C2APB1FZR1_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_C2APB1FZR1_DBG_I2C3_STOP_Pos)

#define	DBGMCU_C2APB1FZR1_DBG_I2C3_STOP DBGMCU_C2APB1FZR1_DBG_I2C3_STOP_Msk

#define	DBGMCU_C2APB1FZR1_DBG_LPTIM1_STOP_Pos (31U)

#define	DBGMCU_C2APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_C2APB1FZR1_DBG_LPTIM1_STOP_Pos

#define	DBGMCU_C2APB1FZR1_DBG_LPTIM1_STOP DBGMCU_C2APB1FZR1_DBG_LPTIM1_STOP_Msk

#define	DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos (5U)

#define	DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos

#define	DBGMCU_APB1FZR2_DBG_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk

#define	DBGMCU_APB1FZR2_DBG_LPTIM3_STOP_Pos (6U)

#define	DBGMCU_APB1FZR2_DBG_LPTIM3_STOP_Msk (0x1UL << DBGMCU_APB1FZR2_DBG_LPTIM3_STOP_Pos

#define	DBGMCU_APB1FZR2_DBG_LPTIM3_STOP DBGMCU_APB1FZR2_DBG_LPTIM3_STOP_Msk

#define	DBGMCU_C2APB1FZR2_DBG_LPTIM2_STOP_Pos (5U)

#define	DBGMCU_C2APB1FZR2_DBG_LPTIM2_STOP_Msk (0x1UL << DBGMCU_C2APB1FZR2_DBG_LPTIM2_STOP_Pos

#define	DBGMCU_C2APB1FZR2_DBG_LPTIM2_STOP DBGMCU_C2APB1FZR2_DBG_LPTIM2_STOP_Msk

#define	DBGMCU_C2APB1FZR2_DBG_LPTIM3_STOP_Pos (6U)

#define	DBGMCU_C2APB1FZR2_DBG_LPTIM3_STOP_Msk (0x1UL << DBGMCU_C2APB1FZR2_DBG_LPTIM3_STOP_Pos

#define	DBGMCU_C2APB1FZR2_DBG_LPTIM3_STOP DBGMCU_C2APB1FZR2_DBG_LPTIM3_STOP_Msk

#define	DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos (11U)

#define	DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos

#define	DBGMCU_APB2FZR_DBG_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk

#define	DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos (17U)

#define	DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos

#define	DBGMCU_APB2FZR_DBG_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk

#define	DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos (18U)

#define	DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos

#define	DBGMCU_APB2FZR_DBG_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk

#define	DBGMCU_C2APB2FZR_DBG_TIM1_STOP_Pos (11U)

#define	DBGMCU_C2APB2FZR_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_C2APB2FZR_DBG_TIM1_STOP_Pos

#define	DBGMCU_C2APB2FZR_DBG_TIM1_STOP DBGMCU_C2APB2FZR_DBG_TIM1_STOP_Msk

#define	DBGMCU_C2APB2FZR_DBG_TIM16_STOP_Pos (17U)

#define	DBGMCU_C2APB2FZR_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_C2APB2FZR_DBG_TIM16_STOP_Pos

#define	DBGMCU_C2APB2FZR_DBG_TIM16_STOP DBGMCU_C2APB2FZR_DBG_TIM16_STOP_Msk

#define	DBGMCU_C2APB2FZR_DBG_TIM17_STOP_Pos (18U)

#define	DBGMCU_C2APB2FZR_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_C2APB2FZR_DBG_TIM17_STOP_Pos

#define	DBGMCU_C2APB2FZR_DBG_TIM17_STOP DBGMCU_C2APB2FZR_DBG_TIM17_STOP_Msk

#define	TIM_CR1_CEN_Pos (0U)

#define	TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)

#define	TIM_CR1_CEN TIM_CR1_CEN_Msk

#define	TIM_CR1_UDIS_Pos (1U)

#define	TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)

#define	TIM_CR1_UDIS TIM_CR1_UDIS_Msk

#define	TIM_CR1_URS_Pos (2U)

#define	TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)

#define	TIM_CR1_URS TIM_CR1_URS_Msk

#define	TIM_CR1_OPM_Pos (3U)

#define	TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)

#define	TIM_CR1_OPM TIM_CR1_OPM_Msk

#define	TIM_CR1_DIR_Pos (4U)

#define	TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)

#define	TIM_CR1_DIR TIM_CR1_DIR_Msk

#define	TIM_CR1_CMS_Pos (5U)

#define	TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)

#define	TIM_CR1_CMS TIM_CR1_CMS_Msk

#define	TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)

#define	TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)

#define	TIM_CR1_ARPE_Pos (7U)

#define	TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)

#define	TIM_CR1_ARPE TIM_CR1_ARPE_Msk

#define	TIM_CR1_CKD_Pos (8U)

#define	TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)

#define	TIM_CR1_CKD TIM_CR1_CKD_Msk

#define	TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)

#define	TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)

#define	TIM_CR1_UIFREMAP_Pos (11U)

#define	TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos)

#define	TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk

#define	TIM_CR2_CCPC_Pos (0U)

#define	TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)

#define	TIM_CR2_CCPC TIM_CR2_CCPC_Msk

#define	TIM_CR2_CCUS_Pos (2U)

#define	TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)

#define	TIM_CR2_CCUS TIM_CR2_CCUS_Msk

#define	TIM_CR2_CCDS_Pos (3U)

#define	TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)

#define	TIM_CR2_CCDS TIM_CR2_CCDS_Msk

#define	TIM_CR2_MMS_Pos (4U)

#define	TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)

#define	TIM_CR2_MMS TIM_CR2_MMS_Msk

#define	TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)

#define	TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)

#define	TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)

#define	TIM_CR2_TI1S_Pos (7U)

#define	TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)

#define	TIM_CR2_TI1S TIM_CR2_TI1S_Msk

#define	TIM_CR2_OIS1_Pos (8U)

#define	TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)

#define	TIM_CR2_OIS1 TIM_CR2_OIS1_Msk

#define	TIM_CR2_OIS1N_Pos (9U)

#define	TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)

#define	TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk

#define	TIM_CR2_OIS2_Pos (10U)

#define	TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)

#define	TIM_CR2_OIS2 TIM_CR2_OIS2_Msk

#define	TIM_CR2_OIS2N_Pos (11U)

#define	TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)

#define	TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk

#define	TIM_CR2_OIS3_Pos (12U)

#define	TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)

#define	TIM_CR2_OIS3 TIM_CR2_OIS3_Msk

#define	TIM_CR2_OIS3N_Pos (13U)

#define	TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)

#define	TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk

#define	TIM_CR2_OIS4_Pos (14U)

#define	TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)

#define	TIM_CR2_OIS4 TIM_CR2_OIS4_Msk

#define	TIM_CR2_OIS5_Pos (16U)

#define	TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos)

#define	TIM_CR2_OIS5 TIM_CR2_OIS5_Msk

#define	TIM_CR2_OIS6_Pos (18U)

#define	TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos)

#define	TIM_CR2_OIS6 TIM_CR2_OIS6_Msk

#define	TIM_CR2_MMS2_Pos (20U)

#define	TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos)

#define	TIM_CR2_MMS2 TIM_CR2_MMS2_Msk

#define	TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos)

#define	TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos)

#define	TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos)

#define	TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos)

#define	TIM_SMCR_SMS_Pos (0U)

#define	TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos)

#define	TIM_SMCR_SMS TIM_SMCR_SMS_Msk

#define	TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos)

#define	TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos)

#define	TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos)

#define	TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos)

#define	TIM_SMCR_OCCS_Pos (3U)

#define	TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos)

#define	TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk

#define	TIM_SMCR_TS_Pos (4U)

#define	TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos)

#define	TIM_SMCR_TS TIM_SMCR_TS_Msk

#define	TIM_SMCR_TS_0 (0x00001UL << TIM_SMCR_TS_Pos)

#define	TIM_SMCR_TS_1 (0x00002UL << TIM_SMCR_TS_Pos)

#define	TIM_SMCR_TS_2 (0x00004UL << TIM_SMCR_TS_Pos)

#define	TIM_SMCR_TS_3 (0x10000UL << TIM_SMCR_TS_Pos)

#define	TIM_SMCR_TS_4 (0x20000UL << TIM_SMCR_TS_Pos)

#define	TIM_SMCR_MSM_Pos (7U)

#define	TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)

#define	TIM_SMCR_MSM TIM_SMCR_MSM_Msk

#define	TIM_SMCR_ETF_Pos (8U)

#define	TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)

#define	TIM_SMCR_ETF TIM_SMCR_ETF_Msk

#define	TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)

#define	TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)

#define	TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)

#define	TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)

#define	TIM_SMCR_ETPS_Pos (12U)

#define	TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)

#define	TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk

#define	TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)

#define	TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)

#define	TIM_SMCR_ECE_Pos (14U)

#define	TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)

#define	TIM_SMCR_ECE TIM_SMCR_ECE_Msk

#define	TIM_SMCR_ETP_Pos (15U)

#define	TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)

#define	TIM_SMCR_ETP TIM_SMCR_ETP_Msk

#define	TIM_DIER_UIE_Pos (0U)

#define	TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)

#define	TIM_DIER_UIE TIM_DIER_UIE_Msk

#define	TIM_DIER_CC1IE_Pos (1U)

#define	TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)

#define	TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk

#define	TIM_DIER_CC2IE_Pos (2U)

#define	TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)

#define	TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk

#define	TIM_DIER_CC3IE_Pos (3U)

#define	TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)

#define	TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk

#define	TIM_DIER_CC4IE_Pos (4U)

#define	TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)

#define	TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk

#define	TIM_DIER_COMIE_Pos (5U)

#define	TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)

#define	TIM_DIER_COMIE TIM_DIER_COMIE_Msk

#define	TIM_DIER_TIE_Pos (6U)

#define	TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)

#define	TIM_DIER_TIE TIM_DIER_TIE_Msk

#define	TIM_DIER_BIE_Pos (7U)

#define	TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)

#define	TIM_DIER_BIE TIM_DIER_BIE_Msk

#define	TIM_DIER_UDE_Pos (8U)

#define	TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)

#define	TIM_DIER_UDE TIM_DIER_UDE_Msk

#define	TIM_DIER_CC1DE_Pos (9U)

#define	TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)

#define	TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk

#define	TIM_DIER_CC2DE_Pos (10U)

#define	TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)

#define	TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk

#define	TIM_DIER_CC3DE_Pos (11U)

#define	TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)

#define	TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk

#define	TIM_DIER_CC4DE_Pos (12U)

#define	TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)

#define	TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk

#define	TIM_DIER_COMDE_Pos (13U)

#define	TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)

#define	TIM_DIER_COMDE TIM_DIER_COMDE_Msk

#define	TIM_DIER_TDE_Pos (14U)

#define	TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)

#define	TIM_DIER_TDE TIM_DIER_TDE_Msk

#define	TIM_SR_UIF_Pos (0U)

#define	TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)

#define	TIM_SR_UIF TIM_SR_UIF_Msk

#define	TIM_SR_CC1IF_Pos (1U)

#define	TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)

#define	TIM_SR_CC1IF TIM_SR_CC1IF_Msk

#define	TIM_SR_CC2IF_Pos (2U)

#define	TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)

#define	TIM_SR_CC2IF TIM_SR_CC2IF_Msk

#define	TIM_SR_CC3IF_Pos (3U)

#define	TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)

#define	TIM_SR_CC3IF TIM_SR_CC3IF_Msk

#define	TIM_SR_CC4IF_Pos (4U)

#define	TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)

#define	TIM_SR_CC4IF TIM_SR_CC4IF_Msk

#define	TIM_SR_COMIF_Pos (5U)

#define	TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)

#define	TIM_SR_COMIF TIM_SR_COMIF_Msk

#define	TIM_SR_TIF_Pos (6U)

#define	TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)

#define	TIM_SR_TIF TIM_SR_TIF_Msk

#define	TIM_SR_BIF_Pos (7U)

#define	TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)

#define	TIM_SR_BIF TIM_SR_BIF_Msk

#define	TIM_SR_B2IF_Pos (8U)

#define	TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos)

#define	TIM_SR_B2IF TIM_SR_B2IF_Msk

#define	TIM_SR_CC1OF_Pos (9U)

#define	TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)

#define	TIM_SR_CC1OF TIM_SR_CC1OF_Msk

#define	TIM_SR_CC2OF_Pos (10U)

#define	TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)

#define	TIM_SR_CC2OF TIM_SR_CC2OF_Msk

#define	TIM_SR_CC3OF_Pos (11U)

#define	TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)

#define	TIM_SR_CC3OF TIM_SR_CC3OF_Msk

#define	TIM_SR_CC4OF_Pos (12U)

#define	TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)

#define	TIM_SR_CC4OF TIM_SR_CC4OF_Msk

#define	TIM_SR_SBIF_Pos (13U)

#define	TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos)

#define	TIM_SR_SBIF TIM_SR_SBIF_Msk

#define	TIM_SR_CC5IF_Pos (16U)

#define	TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos)

#define	TIM_SR_CC5IF TIM_SR_CC5IF_Msk

#define	TIM_SR_CC6IF_Pos (17U)

#define	TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos)

#define	TIM_SR_CC6IF TIM_SR_CC6IF_Msk

#define	TIM_EGR_UG_Pos (0U)

#define	TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)

#define	TIM_EGR_UG TIM_EGR_UG_Msk

#define	TIM_EGR_CC1G_Pos (1U)

#define	TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)

#define	TIM_EGR_CC1G TIM_EGR_CC1G_Msk

#define	TIM_EGR_CC2G_Pos (2U)

#define	TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)

#define	TIM_EGR_CC2G TIM_EGR_CC2G_Msk

#define	TIM_EGR_CC3G_Pos (3U)

#define	TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)

#define	TIM_EGR_CC3G TIM_EGR_CC3G_Msk

#define	TIM_EGR_CC4G_Pos (4U)

#define	TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)

#define	TIM_EGR_CC4G TIM_EGR_CC4G_Msk

#define	TIM_EGR_COMG_Pos (5U)

#define	TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)

#define	TIM_EGR_COMG TIM_EGR_COMG_Msk

#define	TIM_EGR_TG_Pos (6U)

#define	TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)

#define	TIM_EGR_TG TIM_EGR_TG_Msk

#define	TIM_EGR_BG_Pos (7U)

#define	TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)

#define	TIM_EGR_BG TIM_EGR_BG_Msk

#define	TIM_EGR_B2G_Pos (8U)

#define	TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos)

#define	TIM_EGR_B2G TIM_EGR_B2G_Msk

#define	TIM_CCMR1_CC1S_Pos (0U)

#define	TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)

#define	TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk

#define	TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)

#define	TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)

#define	TIM_CCMR1_OC1FE_Pos (2U)

#define	TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)

#define	TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk

#define	TIM_CCMR1_OC1PE_Pos (3U)

#define	TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)

#define	TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk

#define	TIM_CCMR1_OC1M_Pos (4U)

#define	TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos)

#define	TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk

#define	TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos)

#define	TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos)

#define	TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos)

#define	TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos)

#define	TIM_CCMR1_OC1CE_Pos (7U)

#define	TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)

#define	TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk

#define	TIM_CCMR1_CC2S_Pos (8U)

#define	TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)

#define	TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk

#define	TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)

#define	TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)

#define	TIM_CCMR1_OC2FE_Pos (10U)

#define	TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)

#define	TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk

#define	TIM_CCMR1_OC2PE_Pos (11U)

#define	TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)

#define	TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk

#define	TIM_CCMR1_OC2M_Pos (12U)

#define	TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos)

#define	TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk

#define	TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos)

#define	TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos)

#define	TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos)

#define	TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos)

#define	TIM_CCMR1_OC2CE_Pos (15U)

#define	TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)

#define	TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk

#define	TIM_CCMR1_IC1PSC_Pos (2U)

#define	TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)

#define	TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk

#define	TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)

#define	TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)

#define	TIM_CCMR1_IC1F_Pos (4U)

#define	TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)

#define	TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk

#define	TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)

#define	TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)

#define	TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)

#define	TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)

#define	TIM_CCMR1_IC2PSC_Pos (10U)

#define	TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)

#define	TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk

#define	TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)

#define	TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)

#define	TIM_CCMR1_IC2F_Pos (12U)

#define	TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)

#define	TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk

#define	TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)

#define	TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)

#define	TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)

#define	TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)

#define	TIM_CCMR2_CC3S_Pos (0U)

#define	TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)

#define	TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk

#define	TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)

#define	TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)

#define	TIM_CCMR2_OC3FE_Pos (2U)

#define	TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)

#define	TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk

#define	TIM_CCMR2_OC3PE_Pos (3U)

#define	TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)

#define	TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk

#define	TIM_CCMR2_OC3M_Pos (4U)

#define	TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos)

#define	TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk

#define	TIM_CCMR2_OC3M_0 (0x0001UL << TIM_CCMR2_OC3M_Pos)

#define	TIM_CCMR2_OC3M_1 (0x0002UL << TIM_CCMR2_OC3M_Pos)

#define	TIM_CCMR2_OC3M_2 (0x0004UL << TIM_CCMR2_OC3M_Pos)

#define	TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos)

#define	TIM_CCMR2_OC3CE_Pos (7U)

#define	TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)

#define	TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk

#define	TIM_CCMR2_CC4S_Pos (8U)

#define	TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)

#define	TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk

#define	TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)

#define	TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)

#define	TIM_CCMR2_OC4FE_Pos (10U)

#define	TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)

#define	TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk

#define	TIM_CCMR2_OC4PE_Pos (11U)

#define	TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)

#define	TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk

#define	TIM_CCMR2_OC4M_Pos (12U)

#define	TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos)

#define	TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk

#define	TIM_CCMR2_OC4M_0 (0x0001UL << TIM_CCMR2_OC4M_Pos)

#define	TIM_CCMR2_OC4M_1 (0x0002UL << TIM_CCMR2_OC4M_Pos)

#define	TIM_CCMR2_OC4M_2 (0x0004UL << TIM_CCMR2_OC4M_Pos)

#define	TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos)

#define	TIM_CCMR2_OC4CE_Pos (15U)

#define	TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)

#define	TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk

#define	TIM_CCMR2_IC3PSC_Pos (2U)

#define	TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)

#define	TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk

#define	TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)

#define	TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)

#define	TIM_CCMR2_IC3F_Pos (4U)

#define	TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)

#define	TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk

#define	TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)

#define	TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)

#define	TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)

#define	TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)

#define	TIM_CCMR2_IC4PSC_Pos (10U)

#define	TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)

#define	TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk

#define	TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)

#define	TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)

#define	TIM_CCMR2_IC4F_Pos (12U)

#define	TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)

#define	TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk

#define	TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)

#define	TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)

#define	TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)

#define	TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)

#define	TIM_CCMR3_OC5FE_Pos (2U)

#define	TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos)

#define	TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk

#define	TIM_CCMR3_OC5PE_Pos (3U)

#define	TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos)

#define	TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk

#define	TIM_CCMR3_OC5M_Pos (4U)

#define	TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos)

#define	TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk

#define	TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos)

#define	TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos)

#define	TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos)

#define	TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos)

#define	TIM_CCMR3_OC5CE_Pos (7U)

#define	TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos)

#define	TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk

#define	TIM_CCMR3_OC6FE_Pos (10U)

#define	TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos)

#define	TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk

#define	TIM_CCMR3_OC6PE_Pos (11U)

#define	TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos)

#define	TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk

#define	TIM_CCMR3_OC6M_Pos (12U)

#define	TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos)

#define	TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk

#define	TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos)

#define	TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos)

#define	TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos)

#define	TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos)

#define	TIM_CCMR3_OC6CE_Pos (15U)

#define	TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos)

#define	TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk

#define	TIM_CCER_CC1E_Pos (0U)

#define	TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)

#define	TIM_CCER_CC1E TIM_CCER_CC1E_Msk

#define	TIM_CCER_CC1P_Pos (1U)

#define	TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)

#define	TIM_CCER_CC1P TIM_CCER_CC1P_Msk

#define	TIM_CCER_CC1NE_Pos (2U)

#define	TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)

#define	TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk

#define	TIM_CCER_CC1NP_Pos (3U)

#define	TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)

#define	TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk

#define	TIM_CCER_CC2E_Pos (4U)

#define	TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)

#define	TIM_CCER_CC2E TIM_CCER_CC2E_Msk

#define	TIM_CCER_CC2P_Pos (5U)

#define	TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)

#define	TIM_CCER_CC2P TIM_CCER_CC2P_Msk

#define	TIM_CCER_CC2NE_Pos (6U)

#define	TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)

#define	TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk

#define	TIM_CCER_CC2NP_Pos (7U)

#define	TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)

#define	TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk

#define	TIM_CCER_CC3E_Pos (8U)

#define	TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)

#define	TIM_CCER_CC3E TIM_CCER_CC3E_Msk

#define	TIM_CCER_CC3P_Pos (9U)

#define	TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)

#define	TIM_CCER_CC3P TIM_CCER_CC3P_Msk

#define	TIM_CCER_CC3NE_Pos (10U)

#define	TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)

#define	TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk

#define	TIM_CCER_CC3NP_Pos (11U)

#define	TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)

#define	TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk

#define	TIM_CCER_CC4E_Pos (12U)

#define	TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)

#define	TIM_CCER_CC4E TIM_CCER_CC4E_Msk

#define	TIM_CCER_CC4P_Pos (13U)

#define	TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)

#define	TIM_CCER_CC4P TIM_CCER_CC4P_Msk

#define	TIM_CCER_CC4NP_Pos (15U)

#define	TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)

#define	TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk

#define	TIM_CCER_CC5E_Pos (16U)

#define	TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos)

#define	TIM_CCER_CC5E TIM_CCER_CC5E_Msk

#define	TIM_CCER_CC5P_Pos (17U)

#define	TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos)

#define	TIM_CCER_CC5P TIM_CCER_CC5P_Msk

#define	TIM_CCER_CC6E_Pos (20U)

#define	TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos)

#define	TIM_CCER_CC6E TIM_CCER_CC6E_Msk

#define	TIM_CCER_CC6P_Pos (21U)

#define	TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos)

#define	TIM_CCER_CC6P TIM_CCER_CC6P_Msk

#define	TIM_CNT_CNT_Pos (0U)

#define	TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)

#define	TIM_CNT_CNT TIM_CNT_CNT_Msk

#define	TIM_CNT_UIFCPY_Pos (31U)

#define	TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos)

#define	TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk

#define	TIM_PSC_PSC_Pos (0U)

#define	TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)

#define	TIM_PSC_PSC TIM_PSC_PSC_Msk

#define	TIM_ARR_ARR_Pos (0U)

#define	TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)

#define	TIM_ARR_ARR TIM_ARR_ARR_Msk

#define	TIM_RCR_REP_Pos (0U)

#define	TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos)

#define	TIM_RCR_REP TIM_RCR_REP_Msk

#define	TIM_CCR1_CCR1_Pos (0U)

#define	TIM_CCR1_CCR1_Msk (0xFFFFFFFFUL << TIM_CCR1_CCR1_Pos)

#define	TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk

#define	TIM_CCR2_CCR2_Pos (0U)

#define	TIM_CCR2_CCR2_Msk (0xFFFFFFFFUL << TIM_CCR2_CCR2_Pos)

#define	TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk

#define	TIM_CCR3_CCR3_Pos (0U)

#define	TIM_CCR3_CCR3_Msk (0xFFFFFFFFUL << TIM_CCR3_CCR3_Pos)

#define	TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk

#define	TIM_CCR4_CCR4_Pos (0U)

#define	TIM_CCR4_CCR4_Msk (0xFFFFFFFFUL << TIM_CCR4_CCR4_Pos)

#define	TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk

#define	TIM_CCR5_CCR5_Pos (0U)

#define	TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos)

#define	TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk

#define	TIM_CCR5_GC5C1_Pos (29U)

#define	TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos)

#define	TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk

#define	TIM_CCR5_GC5C2_Pos (30U)

#define	TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos)

#define	TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk

#define	TIM_CCR5_GC5C3_Pos (31U)

#define	TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos)

#define	TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk

#define	TIM_CCR6_CCR6_Pos (0U)

#define	TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos)

#define	TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk

#define	TIM_BDTR_DTG_Pos (0U)

#define	TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG TIM_BDTR_DTG_Msk

#define	TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_LOCK_Pos (8U)

#define	TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)

#define	TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk

#define	TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)

#define	TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)

#define	TIM_BDTR_OSSI_Pos (10U)

#define	TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)

#define	TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk

#define	TIM_BDTR_OSSR_Pos (11U)

#define	TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)

#define	TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk

#define	TIM_BDTR_BKE_Pos (12U)

#define	TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)

#define	TIM_BDTR_BKE TIM_BDTR_BKE_Msk

#define	TIM_BDTR_BKP_Pos (13U)

#define	TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)

#define	TIM_BDTR_BKP TIM_BDTR_BKP_Msk

#define	TIM_BDTR_AOE_Pos (14U)

#define	TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)

#define	TIM_BDTR_AOE TIM_BDTR_AOE_Msk

#define	TIM_BDTR_MOE_Pos (15U)

#define	TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)

#define	TIM_BDTR_MOE TIM_BDTR_MOE_Msk

#define	TIM_BDTR_BKF_Pos (16U)

#define	TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos)

#define	TIM_BDTR_BKF TIM_BDTR_BKF_Msk

#define	TIM_BDTR_BK2F_Pos (20U)

#define	TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos)

#define	TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk

#define	TIM_BDTR_BK2E_Pos (24U)

#define	TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos)

#define	TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk

#define	TIM_BDTR_BK2P_Pos (25U)

#define	TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos)

#define	TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk

#define	TIM_BDTR_BKDSRM_Pos (26U)

#define	TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos)

#define	TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk

#define	TIM_BDTR_BK2DSRM_Pos (27U)

#define	TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos)

#define	TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk

#define	TIM_BDTR_BKBID_Pos (28U)

#define	TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos)

#define	TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk

#define	TIM_BDTR_BK2BID_Pos (29U)

#define	TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos)

#define	TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk

#define	TIM_DCR_DBA_Pos (0U)

#define	TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)

#define	TIM_DCR_DBA TIM_DCR_DBA_Msk

#define	TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)

#define	TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)

#define	TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)

#define	TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)

#define	TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)

#define	TIM_DCR_DBL_Pos (8U)

#define	TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)

#define	TIM_DCR_DBL TIM_DCR_DBL_Msk

#define	TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)

#define	TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)

#define	TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)

#define	TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)

#define	TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)

#define	TIM_DMAR_DMAB_Pos (0U)

#define	TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)

#define	TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk

#define	TIM1_OR1_ETR_ADC_RMP_Pos (0U)

#define	TIM1_OR1_ETR_ADC_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC_RMP_Pos)

#define	TIM1_OR1_ETR_ADC_RMP TIM1_OR1_ETR_ADC_RMP_Msk

#define	TIM1_OR1_ETR_ADC_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC_RMP_Pos)

#define	TIM1_OR1_ETR_ADC_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC_RMP_Pos)

#define	TIM1_OR1_TI1_RMP_Pos (4U)

#define	TIM1_OR1_TI1_RMP_Msk (0x1UL << TIM1_OR1_TI1_RMP_Pos)

#define	TIM1_OR1_TI1_RMP TIM1_OR1_TI1_RMP_Msk

#define	TIM2_OR1_TI4_RMP_Pos (2U)

#define	TIM2_OR1_TI4_RMP_Msk (0x3UL << TIM2_OR1_TI4_RMP_Pos)

#define	TIM2_OR1_TI4_RMP TIM2_OR1_TI4_RMP_Msk

#define	TIM2_OR1_TI4_RMP_0 (0x1UL << TIM2_OR1_TI4_RMP_Pos)

#define	TIM2_OR1_TI4_RMP_1 (0x2UL << TIM2_OR1_TI4_RMP_Pos)

#define	TIM2_OR1_ETR_RMP_Pos (1U)

#define	TIM2_OR1_ETR_RMP_Msk (0x1UL << TIM2_OR1_ETR_RMP_Pos)

#define	TIM2_OR1_ETR_RMP TIM2_OR1_ETR_RMP_Msk

#define	TIM16_OR1_TI1_RMP_Pos (0U)

#define	TIM16_OR1_TI1_RMP_Msk (0x3UL << TIM16_OR1_TI1_RMP_Pos)

#define	TIM16_OR1_TI1_RMP TIM16_OR1_TI1_RMP_Msk

#define	TIM16_OR1_TI1_RMP_0 (0x1UL << TIM16_OR1_TI1_RMP_Pos)

#define	TIM16_OR1_TI1_RMP_1 (0x2UL << TIM16_OR1_TI1_RMP_Pos)

#define	TIM17_OR1_TI1_RMP_Pos (0U)

#define	TIM17_OR1_TI1_RMP_Msk (0x3UL << TIM17_OR1_TI1_RMP_Pos)

#define	TIM17_OR1_TI1_RMP TIM17_OR1_TI1_RMP_Msk

#define	TIM17_OR1_TI1_RMP_0 (0x1UL << TIM17_OR1_TI1_RMP_Pos)

#define	TIM17_OR1_TI1_RMP_1 (0x2UL << TIM17_OR1_TI1_RMP_Pos)

#define	TIM1_AF1_BKINE_Pos (0U)

#define	TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos)

#define	TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk

#define	TIM1_AF1_BKCMP1E_Pos (1U)

#define	TIM1_AF1_BKCMP1E_Msk (0x1UL << TIM1_AF1_BKCMP1E_Pos)

#define	TIM1_AF1_BKCMP1E TIM1_AF1_BKCMP1E_Msk

#define	TIM1_AF1_BKCMP2E_Pos (2U)

#define	TIM1_AF1_BKCMP2E_Msk (0x1UL << TIM1_AF1_BKCMP2E_Pos)

#define	TIM1_AF1_BKCMP2E TIM1_AF1_BKCMP2E_Msk

#define	TIM1_AF1_BKINP_Pos (9U)

#define	TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos)

#define	TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk

#define	TIM1_AF1_BKCMP1P_Pos (10U)

#define	TIM1_AF1_BKCMP1P_Msk (0x1UL << TIM1_AF1_BKCMP1P_Pos)

#define	TIM1_AF1_BKCMP1P TIM1_AF1_BKCMP1P_Msk

#define	TIM1_AF1_BKCMP2P_Pos (11U)

#define	TIM1_AF1_BKCMP2P_Msk (0x1UL << TIM1_AF1_BKCMP2P_Pos)

#define	TIM1_AF1_BKCMP2P TIM1_AF1_BKCMP2P_Msk

#define	TIM1_AF1_ETRSEL_Pos (14U)

#define	TIM1_AF1_ETRSEL_Msk (0xFUL << TIM1_AF1_ETRSEL_Pos)

#define	TIM1_AF1_ETRSEL TIM1_AF1_ETRSEL_Msk

#define	TIM1_AF1_ETRSEL_0 (0x1UL << TIM1_AF1_ETRSEL_Pos)

#define	TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos)

#define	TIM1_AF1_ETRSEL_2 (0x4UL << TIM1_AF1_ETRSEL_Pos)

#define	TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos)

#define	TIM2_AF1_ETRSEL_Pos (14U)

#define	TIM2_AF1_ETRSEL_Msk (0xFUL << TIM2_AF1_ETRSEL_Pos)

#define	TIM2_AF1_ETRSEL (0x00003C000)

#define	TIM2_AF1_ETRSEL_0 (0x000004000)

#define	TIM2_AF1_ETRSEL_1 (0x000008000)

#define	TIM2_AF1_ETRSEL_2 (0x000010000)

#define	TIM2_AF1_ETRSEL_3 (0x000020000)

#define	TIM16_AF1_BKINE_Pos (0U)

#define	TIM16_AF1_BKINE_Msk (0x1UL << TIM16_AF1_BKINE_Pos)

#define	TIM16_AF1_BKINE TIM16_AF1_BKINE_Msk

#define	TIM16_AF1_BKCMP1E_Pos (1U)

#define	TIM16_AF1_BKCMP1E_Msk (0x1UL << TIM16_AF1_BKCMP1E_Pos)

#define	TIM16_AF1_BKCMP1E TIM16_AF1_BKCMP1E_Msk

#define	TIM16_AF1_BKCMP2E_Pos (2U)

#define	TIM16_AF1_BKCMP2E_Msk (0x1UL << TIM16_AF1_BKCMP2E_Pos)

#define	TIM16_AF1_BKCMP2E TIM16_AF1_BKCMP2E_Msk

#define	TIM16_AF1_BKINP_Pos (9U)

#define	TIM16_AF1_BKINP_Msk (0x1UL << TIM16_AF1_BKINP_Pos)

#define	TIM16_AF1_BKINP TIM16_AF1_BKINP_Msk

#define	TIM16_AF1_BKCMP1P_Pos (10U)

#define	TIM16_AF1_BKCMP1P_Msk (0x1UL << TIM16_AF1_BKCMP1P_Pos)

#define	TIM16_AF1_BKCMP1P TIM16_AF1_BKCMP1P_Msk

#define	TIM16_AF1_BKCMP2P_Pos (11U)

#define	TIM16_AF1_BKCMP2P_Msk (0x1UL << TIM16_AF1_BKCMP2P_Pos)

#define	TIM16_AF1_BKCMP2P TIM16_AF1_BKCMP2P_Msk

#define	TIM17_AF1_BKINE_Pos (0U)

#define	TIM17_AF1_BKINE_Msk (0x1UL << TIM17_AF1_BKINE_Pos)

#define	TIM17_AF1_BKINE TIM17_AF1_BKINE_Msk

#define	TIM17_AF1_BKCMP1E_Pos (1U)

#define	TIM17_AF1_BKCMP1E_Msk (0x1UL << TIM17_AF1_BKCMP1E_Pos)

#define	TIM17_AF1_BKCMP1E TIM17_AF1_BKCMP1E_Msk

#define	TIM17_AF1_BKCMP2E_Pos (2U)

#define	TIM17_AF1_BKCMP2E_Msk (0x1UL << TIM17_AF1_BKCMP2E_Pos)

#define	TIM17_AF1_BKCMP2E TIM17_AF1_BKCMP2E_Msk

#define	TIM17_AF1_BKINP_Pos (9U)

#define	TIM17_AF1_BKINP_Msk (0x1UL << TIM17_AF1_BKINP_Pos)

#define	TIM17_AF1_BKINP TIM17_AF1_BKINP_Msk

#define	TIM17_AF1_BKCMP1P_Pos (10U)

#define	TIM17_AF1_BKCMP1P_Msk (0x1UL << TIM17_AF1_BKCMP1P_Pos)

#define	TIM17_AF1_BKCMP1P TIM17_AF1_BKCMP1P_Msk

#define	TIM17_AF1_BKCMP2P_Pos (11U)

#define	TIM17_AF1_BKCMP2P_Msk (0x1UL << TIM17_AF1_BKCMP2P_Pos)

#define	TIM17_AF1_BKCMP2P TIM17_AF1_BKCMP2P_Msk

#define	TIM1_AF2_BK2INE_Pos (0U)

#define	TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos)

#define	TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk

#define	TIM1_AF2_BK2CMP1E_Pos (1U)

#define	TIM1_AF2_BK2CMP1E_Msk (0x1UL << TIM1_AF2_BK2CMP1E_Pos)

#define	TIM1_AF2_BK2CMP1E TIM1_AF2_BK2CMP1E_Msk

#define	TIM1_AF2_BK2CMP2E_Pos (2U)

#define	TIM1_AF2_BK2CMP2E_Msk (0x1UL << TIM1_AF2_BK2CMP2E_Pos)

#define	TIM1_AF2_BK2CMP2E TIM1_AF2_BK2CMP2E_Msk

#define	TIM1_AF2_BK2INP_Pos (9U)

#define	TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos)

#define	TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk

#define	TIM1_AF2_BK2CMP1P_Pos (10U)

#define	TIM1_AF2_BK2CMP1P_Msk (0x1UL << TIM1_AF2_BK2CMP1P_Pos)

#define	TIM1_AF2_BK2CMP1P TIM1_AF2_BK2CMP1P_Msk

#define	TIM1_AF2_BK2CMP2P_Pos (11U)

#define	TIM1_AF2_BK2CMP2P_Msk (0x1UL << TIM1_AF2_BK2CMP2P_Pos)

#define	TIM1_AF2_BK2CMP2P TIM1_AF2_BK2CMP2P_Msk

#define	RSSLIB_HDP_AREA_Pos (0U)

#define	RSSLIB_HDP_AREA_Msk (0x3UL << RSSLIB_HDP_AREA_Pos)

#define	RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA_Pos)

#define	RSSLIB_HDP_AREA1 RSSLIB_HDP_AREA1_Msk

#define	RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE)

#define	IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC)

#define	IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC_COMMON)

#define	IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES)

#define	IS_COMP_ALL_INSTANCE(INSTANCE)

#define	IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)

#define	IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)

#define	IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)

#define	IS_DMA_ALL_INSTANCE(INSTANCE)

#define	IS_GPIO_ALL_INSTANCE(INSTANCE)

#define	IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)

#define	IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)

#define	IS_I2C_ALL_INSTANCE(INSTANCE)

#define	IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)

#define	IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)

#define	IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI2)

#define	IS_IPCC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IPCC)

#define	IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)

#define	HSEM_CPU1_COREID (0x00000004U) /* Semaphore Core ID */

#define	HSEM_CPU2_COREID (0x00000008U) /* Semaphore Core ID */

#define	HSEM_SEMID_MIN (0U) /* HSEM ID Min*/

#define	HSEM_SEMID_MAX (15U) /* HSEM ID Max */

#define	HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */

#define	HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */

#define	HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */

#define	HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */

#define	IS_PKA_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PKA)

#define	IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)

#define	IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)

#define	IS_TAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TAMP)

#define	IS_SPI_ALL_INSTANCE(INSTANCE)

#define	IS_SUBGHZ_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SUBGHZSPI)

#define	IS_SUBGHZ_MODULATION_SUPPORTED(COMMAND, PACKET_TYPE) (1U == 1U)

#define	IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)

#define	IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)

#define	IS_LPTIM_INSTANCE(INSTANCE)

#define	IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)

#define	IS_TIM_INSTANCE(INSTANCE)

#define	IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)

#define	IS_TIM_BREAK_INSTANCE(INSTANCE)

#define	IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE)

#define	IS_TIM_BKIN2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)

#define	IS_TIM_CC1_INSTANCE(INSTANCE)

#define	IS_TIM_CC2_INSTANCE(INSTANCE)

#define	IS_TIM_CC3_INSTANCE(INSTANCE)

#define	IS_TIM_CC4_INSTANCE(INSTANCE)

#define	IS_TIM_CC5_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)

#define	IS_TIM_CC6_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)

#define	IS_TIM_DMA_INSTANCE(INSTANCE)

#define	IS_TIM_DMA_CC_INSTANCE(INSTANCE)

#define	IS_TIM_DMABURST_INSTANCE(INSTANCE)

#define	IS_TIM_TISEL_INSTANCE(INSTANCE)

#define	IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL)

#define	IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL)

#define	IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)

#define	IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)

#define	IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)

#define	IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)

#define	IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)

#define	IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)

#define	IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)

#define	IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)

#define	IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)

#define	IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)

#define	IS_TIM_ETR_INSTANCE(INSTANCE)

#define	IS_TIM_ETRSEL_INSTANCE(INSTANCE)

#define	IS_TIM_MASTER_INSTANCE(INSTANCE)

#define	IS_TIM_SLAVE_INSTANCE(INSTANCE)

#define	IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)

#define	IS_TIM_REMAP_INSTANCE(INSTANCE)

#define	IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)

#define	IS_TIM_TRGO2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)

#define	IS_TIM_XOR_INSTANCE(INSTANCE)

#define	IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))

#define	IS_UART_INSTANCE(INSTANCE)

#define	IS_USART_INSTANCE(INSTANCE)

#define	IS_UART_HWFLOW_INSTANCE(INSTANCE)

#define	IS_SMARTCARD_INSTANCE(INSTANCE)

#define	IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE)

#define	IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)

#define	IS_UART_LIN_INSTANCE(INSTANCE)

#define	IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)

#define	IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)

#define	IS_UART_SPI_SLAVE_INSTANCE(INSTANCE)

#define	IS_UART_FIFO_INSTANCE(INSTANCE)

#define	IS_IRDA_INSTANCE(INSTANCE)

#define	IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)

Typedefs
typedef void(*	RSSLIB_S_CloseExitHDP_t) (uint32_t hdp_area, uint32_t jump_addr)
	Prototype of RSSLIB Close and exit HDP Function @detail This function close the requested hdp area passed in input parameter and jump to the reset handler present within the Vector table. The function does not return on successful execution.

Enumerations
enum	IRQn_Type { NonMaskableInt_IRQn = -14 , HardFault_IRQn = -13 , MemoryManagement_IRQn = -12 , BusFault_IRQn = -11 , UsageFault_IRQn = -10 , SVCall_IRQn = -5 , DebugMonitor_IRQn = -4 , PendSV_IRQn = -2 , SysTick_IRQn = -1 , WWDG_IRQn = 0 , PVD_PVM_IRQn = 1 , TAMP_STAMP_LSECSS_SSRU_IRQn = 2 , RTC_WKUP_IRQn = 3 , FLASH_IRQn = 4 , RCC_IRQn = 5 , EXTI0_IRQn = 6 , EXTI1_IRQn = 7 , EXTI2_IRQn = 8 , EXTI3_IRQn = 9 , EXTI4_IRQn = 10 , DMA1_Channel1_IRQn = 11 , DMA1_Channel2_IRQn = 12 , DMA1_Channel3_IRQn = 13 , DMA1_Channel4_IRQn = 14 , DMA1_Channel5_IRQn = 15 , DMA1_Channel6_IRQn = 16 , DMA1_Channel7_IRQn = 17 , ADC_IRQn = 18 , DAC_IRQn = 19 , C2SEV_PWR_C2H_IRQn = 20 , COMP_IRQn = 21 , EXTI9_5_IRQn = 22 , TIM1_BRK_IRQn = 23 , TIM1_UP_IRQn = 24 , TIM1_TRG_COM_IRQn = 25 , TIM1_CC_IRQn = 26 , TIM2_IRQn = 27 , TIM16_IRQn = 28 , TIM17_IRQn = 29 , I2C1_EV_IRQn = 30 , I2C1_ER_IRQn = 31 , I2C2_EV_IRQn = 32 , I2C2_ER_IRQn = 33 , SPI1_IRQn = 34 , SPI2_IRQn = 35 , USART1_IRQn = 36 , USART2_IRQn = 37 , LPUART1_IRQn = 38 , LPTIM1_IRQn = 39 , LPTIM2_IRQn = 40 , EXTI15_10_IRQn = 41 , RTC_Alarm_IRQn = 42 , LPTIM3_IRQn = 43 , SUBGHZSPI_IRQn = 44 , IPCC_C1_RX_IRQn = 45 , IPCC_C1_TX_IRQn = 46 , HSEM_IRQn = 47 , I2C3_EV_IRQn = 48 , I2C3_ER_IRQn = 49 , SUBGHZ_Radio_IRQn = 50 , AES_IRQn = 51 , RNG_IRQn = 52 , PKA_IRQn = 53 , DMA2_Channel1_IRQn = 54 , DMA2_Channel2_IRQn = 55 , DMA2_Channel3_IRQn = 56 , DMA2_Channel4_IRQn = 57 , DMA2_Channel5_IRQn = 58 , DMA2_Channel6_IRQn = 59 , DMA2_Channel7_IRQn = 60 , DMAMUX1_OVR_IRQn = 61 }
	stm32wl55xx Interrupt Number Definition, according to the selected device in Library_configuration_section More...

Detailed Description

CMSIS Cortex Device Peripheral Access Layer Header File. This file contains all the peripheral register's definitions, bits definitions and memory mapping for stm32wl55xx devices.

Author: MCD Application Team

This file contains:selected

Data structures and the address mapping for all peripherals
Peripheral's registers declarations and bits definition
Macros to access peripheral's registers hardware

Attention

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32wl55xx.h.

SHUBv3_MLC_DatalogFusion_GUI 0.2.6 ISCA Lab, HMU

Data Structures

Macros

Typedefs

Enumerations

Detailed Description